Design Guide

Platform Design Checklist
R
Intel
®
855GM/855GME Chipset Platform Design Guide 309
16.7.11. LAN Interface
Pin Name System
Pull-up/Pull-down
Notes
9
LAN_JCLK Connect to LAN_CLK on the platform LAN Connect Device. If LAN interface is
not used, leave the signal unconnected (NC).
LAN_RST#
10 k
Ω pull-down to
gnd
If ICH4-M LAN not
used
Timing Requirement: Signal should be connected to power monitoring logic, and
should go high no sooner than 10 ms after both VccSus3_3 and VccSus1_5
have reached their nominal voltages.
NOTE: If ICH4-M LAN controller is NOT used, pull LAN_RST# down through a
10 k
Ω resistor.
LAN_RXD[2:0],
LAN_TXD[2:0]
Connect to LAN_RXD on the platform LAN Connect Device.
If LAN interface is not used, leave the signal unconnected (NC)
LAN_RSTYSNC Connect to LAN_RSTSYNC on Platform LAN Connect Devce.
If LAN interface is not used, leave the signal unconnected (NC).
16.7.12. Primary IDE Interface
Pin Name System
Pull-up/Pull-
down
Series
Damping
Notes
9
IDE_PDD[15:0]
These signals have integrated series resistors.
IDE_PDA[2:0],
IDE_PDCS1#,
IDE_PDCS3#,
IDE_PDDACK#,
IDE_PDIOW#,
IDE_PDIOR#
These signals have integrated series resistors. Pads for series resistors can
be implemented should the system designer have signal integrity concerns.
IDE_PDDREQ These signals have integrated series resistors and pull-down resistors in
ICH4-M.
IDE_PIORDY
4.7 k
Ω pull-up
to Vcc3_3
This signal has integrated series resistor in ICH4-M.