Design Guide

A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
SO-DIMM 0
Power plane for Serial Presence Detect logic
Layout note: Place capacitors between and near DDR connector if possible.
4.401
DDR SO-DIMMs (1 of 2)
A
11 50Monday, September 15, 2003
Intel 855GM/GME CRB <Doc>
Title
Size Document Number Rev
Date: Sheet
of
Project:
M_CB_R7
M_DATA_R_61
M_DATA_R_52
M_CB_R0
M_DATA_R_53
M_DATA_R_48
M_DATA_R_37
M_DATA_R_1
M_DATA_R_45
M_DATA_R_12
M_DATA_R_54
M_DQS_R4
M_DATA_R_50
M_DATA_R_46
M_DQS_R1
M_CB_R4
M_DATA_R_33
M_DATA_R_43
M_DATA_R_51
M_DATA_R_26
M_CB_R5
M_DATA_R_59
M_DATA_R_35
M_DATA_R_0
M_DATA_R_22
M_CB_R2
M_DQS_R2
M_DQS_R0
M_DATA_R_30
M_DATA_R_25
M_DATA_R_56
M_DATA_R_44
M_DATA_R_5
M_DQS_R5
M_DATA_R_15
M_DATA_R_8
M_DATA_R_20
M_DATA_R_27
M_DQS_R7
M_DATA_R_57
M_DATA_R_21M_CB_R3
M_DATA_R_2
M_DATA_R_10
M_DATA_R_32
M_DATA_R_49
M_DATA_R_19
M_DATA_R_18
M_DATA_R_31
M_CB_R6
M_DATA_R_62
M_DATA_R_39
M_DATA_R_40
M_DATA_R_7
M_DATA_R_36
M_DATA_R_42
M_DATA_R_23
M_DQS_R3
M_DQS_R6
M_DATA_R_9
M_DATA_R_24
M_DATA_R_17
M_DATA_R_58
M_DATA_R_41
M_CB_R1
M_DATA_R_38
M_DATA_R_11
M_DATA_R_47
M_DATA_R_60
M_DATA_R_3
M_DATA_R_14
M_DATA_R_63
M_DATA_R_55
M_DATA_R_34
M_DQS_R8
M_DATA_R_29
M_DATA_R_4
M_DATA_R_28
M_DATA_R_13
M_DATA_R_16
M_DATA_R_6
M_DM_R_0
M_DM_R_1
M_DM_R_2
M_DM_R_3
M_DM_R_4
M_DM_R_5
M_DM_R_6
M_DM_R_7
M_DM_R_8
M_AA_FR_3
M_AA1
M_AA_FR_11
M_AA_FR_6
M_AA_FR_8
M_AA_FR_12
M_AA_FR_0
M_AA_FR_10
M_AA_FR_9
M_AA4
M_AA5
M_AA_FR_7
M_AA2
+V3.3S_SPD12
M_CAS_FR#13
M_BS0_FR#13
M_CLK_DDR07
M_CLK_DDR0#7
M_DQS_R[8:0]12..14
M_DATA_R_[63:0]12..14
M_CLK_DDR17
M_CLK_DDR1#7
M_BS1_FR#13
M_CLK_DDR2#7
M_CS1#7,12,14
M_RAS_FR#13
SMB_CLK_S6,8,12,16,18
M_CB_R[7:0]12..14
M_CKE17,12,14
SMB_DATA_S6,8,12,16,18
M_CS0#7,12,14
M_CLK_DDR27
M_CKE07,12,14
M_WE_FR#13
+V3.3S5,6,8,9,15..18,20,21,23,26,31,33..36,38..40,45
SM_VREF_DIMM12,44
+V2.5_DDR 12,44,46
+V2.59,12,44
M_DM_R_[8:0]12..14
M_AA[5:4]7,14
M_AA_FR_313
M_AA_FR_013
M_AA[2:1]7,14
M_AA_FR_[12:6]13
+V3.3S_SPD12
+V2.5_DDR12,44,46
SO-DIMM_RSVD_FR
C5W5
0.1UF
R4W1 0.01_1%
C6W8
0.1UF
C4G2
150uF
C5W6
0.1UF
C4G1
150uF
C6V2
0.1UF
C4W3
0.1UF
C5W3
0.1UF
C5W4
0.1UF
C4W2
0.1UF
R4F1
0.01_1%
J6H1A CON200_DDR-SODIMM
112
111
110
109
108
107
106
105
102
101
115
100
99
97
117
116
98
71
73
79
83
72
74
80
84
35
37
158
160
89
91
96
95
120
118
119
121
122
194
196
198
195
193
86
12
26
48
62
134
148
170
184
78
11
25
47
61
133
147
169
183
77
5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13(DU)
BA0
BA1
BA2(DU)
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0
CK0#
CK1#
CK1
CK2
CK2#
CKE0
CKE1
CAS#
RAS#
WE#
S0#
S1#
SA0
SA1
SA2
SCL
SDA
RESET(DU)
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
J6H1B CON200_DDR-SODIMM
9
21
33
45
57
69
81
93
113
131
143
155
157
167
179
191
10
22
34
36
46
58
70
82
92
94
114
132
144
156
168
180
192
199
197
1
2
3
15
27
39
51
63
75
87
103
125
137
149
159
161
173
185
4
16
28
38
40
52
64
76
88
90
104
126
138
150
162
174
186
85
123
124
200
201
202
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDDID
VDDSPD
VREF1
VREF2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
DU1
DU2
DU3
DU4
GND0
GND1
C6W2
0.1UF