Design Guide

A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
IDE Activity LEDs
For
Secondary
IDE Drive
Only
Note: Primary IDE
Power on Turner
DC/DC Module
MDC Interposer Header
Layout Note:
Place R9F3, R9F7 and R9G2
0.1 to 0.4 inches from MDC
header based on topology
Secondary IDE Power
SPARE GATE
4.401
IDE 2 of 2 / MDC INTERPOSER
A
27 50
Monday, September 15, 2003
Intel 855GM/GME CRB
<Doc>
Title
Size Document Number Rev
Date: Sheet
of
Project:
IDE_SPWR2_D
IDE_SPWR2
SDATAIN0_D
V5S_IDE_PD
SDATAIN2_D
SHMIDT2
SHMIDT3
AC_BITCLK_D
AC_SDATAOUT_D
SHMIDT4
IDE_SRST#
IDE_SPWR_EN_Q#
IDE_SPWR_EN_D#
SDATAIN1_D
TP_SHMIDT_C
IDE_SPWR_EN
IDE_SPWR_EN
IDE_SPWR_EN#
IDE_SDACTIVE#_Q
IDE_PLED
AC_SYNC19
AUDIO_PWRDN19 AC_SPKR 19
AC_RST# 19
AC_SDATAOUT 19
AC_BITCLK19
+V520..23,36,37,44,45
+V3.315,18..20,23,30,32,35,37,38,44,45
+V3.3ALWAYS5,15,19..23,28,29,32,36..39,45
+V5S8,15..18,20,23..25,33..35,38..40,45,46
+V5S_IDE_S
+V5S8,15..18,20,23..25,33..35,38..40,45,46
+V5S8,15..18,20,23..25,33..35,38..40,45,46
AC_SDATAIN2 19
AC_SDATAIN019
AC_SDATAIN119
IDE_SPWR_EN#34,37
+V5S_IDE_S
IDE_D_SRST# 26
+V12S15,17,23,37,45
+V12S_IDE_S
+V5S8,15..18,20,23..25,33..35,38..40,45,46
+V5S_IDE_S
+V5S8,15..18,20,23..25,33..35,38..40,45,46
IDE_SDACTIVE#26
IDE_PDACTIVE#26,45
+V12S_IDE_S
R2G14
100K
R2J3
470
C2H1
0.1UF
J2H1
4Pin_PwrConn
1
2
3
4
R9F5
33
Q3G1
2N7002
3
1
2
R2H5
1M
U2H1A
SI4925DY
1
2
7 8
C2J1
22UF
C2G14
1000PF
R9G2 33
C2W1
0.1UF
DS2J2
GREEN
1 2
C2W3
0.1UF
R3H2
47
U3H1A
74HC14
1 2
147
J9F4
2x10-SHD-HDR
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
20
18
R2W1
1M
U3H1C
74HC14
5 6
147
R9F3 33
C2W2
0.1UF
U3H1E
74HC14
11 10
147
U2H1B
SI4925DY
3
4
5 6
R2H8
100K
R2H1
NO_STUFF_0
C2H2
1000PF
R2G15
1M
DS2J1
GREEN
1 2
R2H6
390K
R3H1
0
R9F7 33
U3H1B
74HC14
3 4
147
R9F2
10K
SI2307DS
Q2G4
1
3 2
U3H1D
74HC14
9 8
147
R2H7
0.01_1%
R9F6
33
Q3H1
BSS138
<NO_STUFF>
3
1
2
+
C2H3
100uF
R2J6
470