Design Guide

General Design Considerations
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855GM/855GME Chipset Platform Design Guide 35
of the motherboard. Due to the arrangement of the processor and the GMCH pin-maps, GND vias
placed near all GND land pads will also be very close to high-speed signals that may be
transitioning to an internal layer. Thus, no additional ground stitching vias (besides the GND pin
vias) are required in the immediate vicinity of the processor and the GMCH packages to
accompany the signal transitions from the component side into an internal layer.
6. High-speed routing on external layers should be minimized in order to avoid EMI. Routing on
external layers also introduces different delays compared to internal layers. This makes it
extremely difficult to do length matching if routing is done on both internal and external layers.
7. If Intel’s recommended stackup guidelines are not used, then the OEM is liable for all aspects of
their board design (i.e. understanding impacts of SI and power distribution).