Design Guide
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
LPC POWERED ON SUSPEND RAIL FOR ADD-IN H8 CARD
Layout Note:
Line up LPC slot
with PCI Slot 3
SIO Sidebands
LPC Debug Slot
GROUND
HEADERS
TEST HEADER
SMC Sidebands for LPC Power Management
NO STUFF
ICH4-M Testpoint Header
4.401
LPC Slot & Debug Headers
A
37 50Monday, September 15, 2003
Intel 855GM/GME CRB <Doc>
Title
Size Document Number Rev
Date: Sheet
of
Project:
LPC_RST#
R4169_D
H_DPSLP#3,7,18
+V5
20..23,27,36,44,45
SUS_CLK19,33
ICH_MFG_MODE19
FWH_WP# 19,31
FWH_TBL# 19,31
+V5_LPCSLOT
+V3.3ALWAYS_ICH20,21
+V520..23,27,36,44,45
PM_STPPCI# 6,19
INT_SERIRQ 18,22..24,32,34
PM_CPUPERF#19
CLK_LPC146
+V3.3_LPCSLOT
CLK_LPCPCI 6
+V3.3_LPCSLOT
LPC_AD219,31..34
LPC_AD3 19,31..34
PM_SLP_S5#19,38
PCI_PME#15,18,22,23
DELAYED_VR_PWRGD 19,39
LPC_DRQ#119
+V3.3ALWAYS5,15,19..23,27..29,32,36,38,39,45
H_RCIN#18,32
PCI_GATED_RST#22,23,32
INT_PIRQH#18,21..23
PM_SLP_S4# 19,20,32,38,44,45
VR_PWRGD7,39
+V5_LPCSLOT
PM_STPCPU#6,19,39
LPC_AD1 19,31..34
IDE_SATADET 19,26
PM_DPRSLPVR19,39
+V3.3S_ICH19..22,24
LPC_FRAME#19,31..34
+V12S15,17,23,27,45
SMC_EXTSMI#19,32,34,36
IDE_SPWR_EN#27,34
PM_SUS_STAT# 19,32,34
BUF_PCI_RST# 18,22..24,26,31,32,34
SMC_EXTSMI#19,32,34,36
+V3.3_LPCSLOT
PM_CLKRUN# 19,21..24,32,34
IDE_PATADET 19,26
+V3.3 15,18..20,23,27,30,32,35,38,44,45
+V5_LPCSLOT
PM_SLP_S1#6,19,38,45
PM_SUS_CLK 15,19
LPC_DRQ#0 19
INT_IRQ14 18,21,26
AGP_SUSPEND# 19
PM_C3_STAT#19
LPC_AD019,31..34
INT_IRQ15 18,21,26
PM_GMUXSEL 19
PM_CLKRUN# 19,21..24,32,34
ICH_GPIO719
PCI_PME# 15,18,22,23
KBC_A20GATE32,36
+V12S15,17,23,27,45
SMB_SB_DATA 32,36,45
SMB_THRM_DATA 5,32
SMB_SB_CLK 32,36,45
SMB_THRM_CLK 5,32
BUF_PCI_RST# 18,22..24,26,31,32,34
SMB_SB_ALRT# 32,36,45
SMB_SC_INT# 32
AC_PRESENT#32,45
H_STPCLK# 3,18
H_CPUSLP# 3,18
DOCK_INTR#24,32,36
PM_PWROK19,21,25,32,39
PM_RI#19,21,35
PM_SLP_S3#19,25,32,38,44,45
H_SMI#3,18
SMC_ONOFF#32,45
SM_INTRUDER#18,21
SMB_ALERT#18,21
H_NMI3,18
H_INIT# 3,18
H_INTR 3,18
SMC_RSTGATE#32
H_PWRGD3,18
FAN_ON 32,38
SMC_RUNTIME_SCI# 19,32,36
SMC_WAKE_SCI# 19,32,36
PM_BATLOW# 19,32,36
PM_PWRBTN#19,32
PM_THRM#5,19,21,32
BAT_SUSPEND32
PM_RSMRST#19,21,32
GATED_SMC_SHUTDOWN45
VR_ON32
J9D2
15x2_HDR
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
R7J4 10K
C9G2
22UF
J7E1
1 2
R9G1 0.01_1%
R7J3
4.7K
J9J1
2X8_HDR
2
4
6
8
1
3
5
7
9
11
13
15
10
12
14
16
J7F2
1 2
J9E1
1 2
C9G4
22UF
J3H1
2X8_HDR
2
4
6
8
1
3
5
7
9
11
13
15
10
12
14
16
J2A2
1 2
J2J2
8Pin HDR
1 2
3 4
5 6
7 8
R9G3
NO_STUFF_0
C8F3
0.1UF
R9G5 0.01_1%
J2J1
8Pin HDR
1 2
3 4
5 6
7 8
C8F1
0.1UF
R3H3 1K
C9G1
0.1UF
J9J4
1 2
J9J3
1 2
R9G4
0
KEY
J8F1
60Pin_CardCon
B1 A1
B2 A2
B3
B4
A3
B5
A4
B6
B7
A5
B8
A6
B9
B10
A7
B11
A8
B12
B13
A9
B14
A10
B15
B16
A11
B17
A12
B18
B20
A13
B21
A14
B22
B23
A15
B19
B24
A16
B25
B26
A17
B27
A18
B28
A20
B29
A21
B30
A22
A19
A23
A24
A25
A26
A27
A28
A29
A30
12V1 12V2
SUSCLK NEG_12V
GND1
LREQ
GND2
VCC3_1
BP_CLK
LCNTL0
GND3
VCC3_2
LDC
LCNTL1
LD5
GND4
GND5
LD3
LD6
LD1
GND6
LD4
3V_STBY
GND7
LPS
KBRESTE#
LD2
A20GATE#
LD0
GND8
VCC5_1
VCC5_2
LDRQ1#
SCLK
LFRAME1#
GND9
GND10
LSMI#
LAD2
SERIRQ
LAD0
GND11
CLKRUN#
PCIRST#
GND12
GND13
VCC5_3
OSC
LDRQ0#
VCC3_3
GND14
LINK_ON
LAD3
LAD1
GND15
PCICLK
LPCPD#
GND16
PME#
VCC3_4
J1H6
1 2
C9G3
0.1UF
J7J1
2X5-Header
1
3 4
2
5
7
9 10
8
6
J1E2
1 2
J7A1
1 2