Design Guide
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Step 1 - Power OK
Note: J1H1 enables
Manual VID strapping
With pin 13 high, B input goes to C
output. With pin 13 low, A input goes
to C output.
Step 2 - VR ON
Step 3 - Power Good
VR PWRGD CIRCUIT
Steelcliff Headers
0
S0
1
1
Connector 2
(rows C,D)
Output
1
S2
Connector 1
(rows A,B)
1B
S1
VR Interposer Headers
1
A
Input
C
C
<Doc> 4.401
Processor VR Interposer Support & Power Circuitry
A
39 50Monday, September 15, 2003
Intel 855GM/GME CRB
Title
Size Document Number Rev
Date: Sheet
of
Project:
PWRGD2
OFF_BOARD_VR_ON
OPAMP_N
OPAMP_P
MAIN2_PWROK
PWRGD1
MAIN_PWROK
INTERPOSER_PRES#
OFF_BOARD_VR_PWRGD
OPAMP_EN
SC_PSI
OFF_BOARD_VR_ON
S2_S1
IMVP-4Strap_VID0
MUX_SWITCH
INTERPOSER_PRES
IMVP_PWRGD_D
INTERPOSER_PRES#
INTERPOSER_PRES#
PM_STPCPU# 6,19,37
PM_DPRSLPVR 19,37
PM_PSI# 3
VR_VID3 40
VR_VID4 40
VR_VID5 40
DDR_VR_PWRGD44
VR_SHUT_DOWN#32
CORE_VR_ON
PWR_PWROK45
V1.5_PWRGD20
ON_BOARD_VR_PWRGD
V5A_PWRGD21
VR_VID040
VR_VID140
VR_VID240
+V3.3S
5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,45
+VDC 16,21,45
+V5S
8,15..18,20,23..25,27,33..35,38,40,45,46
+V5S8,15..18,20,23..25,27,33..35,38,40,45,46
+V5S8,15..18,20,23..25,27,33..35,38,40,45,46
+V3.3S
5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,45
+V3.3S5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,45
ON_BOARD_VR_ON
PM_PWROK 19,21,25,32,37
VR_PWRGD 7,37
DELAYED_VR_PWRGD 19,37
+V5S
8,15..18,20,23..25,27,33..35,38,40,45,46
VR_PWRGD_CK408# 6
+V3.3ALWAYS5,15,19..23,27..29,32,36..38,45
+V3.3ALWAYS5,15,19..23,27..29,32,36..38,45
+V3.3ALWAYS5,15,19..23,27..29,32,36..38,45
+V3.3S5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,45
+V3.3ALWAYS5,15,19..23,27..29,32,36..38,45
IMVP-4Strap_VID246
IMVP-4Strap_VID346
+V3.3S5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,45
+V5S8,15..18,20,23..25,27,33..35,38,40,45,46
IMVP-4Strap_VID446
+V3.3S
5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,45
IMVP-4Strap_VID546
IMVP-4Strap_VID146
+V3.3S5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,45
+V3.3S5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,45
VR_VID0 40
VR_VID1 40
VR_VID2 40
VR_VID3 40
VR_VID4 40
VR_VID5 40
H_VID04
H_VID14
H_VID24
H_VID34
H_VID44
H_VID54
+V3.3S 5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,45
+V5S 8,15..18,20,23..25,27,33..35,38,40,45,46
R6C6
2K_1%
C1G1
0.01UF
J1H1
2X8_HDR
2
4
6
8
1
3
5
7
9
11
13
15
10
12
14
16
C4B5
0.1UF
R1G5
10K
U4B3B
74HC00
4
5
6
7
14
U7A3
74AHC1G08
1
2
4
53
U4B3A
74HC00
1
2
3
7
14
R1G10
8.2K
C7A4
0.1UF
R1G6
8.2K
Q6C1
BSS84
1
3
2
R1G8
8.2K
C4B2
0.1UF
R3G11
10K
R4N3
100K
C7B1
0.1UF
J5C2
20x2_Header
21
4
6
3
8
10
5
12
14
7
16
9
11
13
15
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
R6C4
1.58K
1%
U4B3C
74HC00
10
9
8
7
14
R6C9
10K
R1G11
8.2K
U4B5
74AHC1G08
1
2
4
53
J5C1
20x2_Header
21
4
6
3
8
10
5
12
14
7
16
9
11
13
15
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
R1G7
8.2K
R2G13
10K
R5C4
0
R4N2
2.2k
U7A5
74AHC1G08
1
2
4
53
C7A2
0.1UF
U7B1
74AHC1G08
1
2
4
53
R6C10
10K
C6C6
0.1UF
C4B6
0.1UF
R1G9
8.2K
Q2G1
2N3904
1
3
2
R1H3
8.2K
U4B4
74AHC1G08
1
2
4
53
VDD+
GND
-
+
U6C1A
TLV2463
1
3
2
4
5
10
U4B3D
74HC00
13
12
11
7
14
C6C4
1uF
20%
U1G1
74CBT16209A
2
5
8
11
13
3
6
9
12
14
1
48
46
44
41
38
36
45
43
40
37
35
7
4
16
18
21
23
17
19
22
24
33
31
28
26
32
30
27
25
47 10
15
20
34
39
2942
A0
A1
A2
A3
A4
B0
B1
B2
B3
B4
S0
S1
C0
C1
C2
C3
C4
D0
D1
D2
D3
D4
VCC
GND0
A5
A6
A7
A8
B5
B6
B7
B8
C5
C6
C7
C8
D5
D6
D7
D8
S2 GND1
GND2
GND3
GND5
GND6
GND4GND7