Design Guide

A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
MASTER_RESET#
U7A5
PG 39
PM_PWROK
DC/DC
Turner
ITP
PG 5
PWR_PWROK
PG 32
SMC
DOCKING
PG 25
ICH4
PG 19
CPU
PG 3
GMCH
PG 8
PCI_RST_SLOTS#
PCI
SLOTS
PG 22
H_CPURST#
PG 41
Core VR
U8A2
PG 32
MAX809
PG 33
PCI_RST#
SMC_RST#
SMC_RES#
SMC_PROG_RST#
H_PWRGD
Reset Map
PG 45
PG 45
SW8J1
PS_ON_SW#
SMC_SHUTDOWN
PM_RSMRST#
ADD
CONN
PG 15
LPC
SLOT
PG 37
PG32
Q9B3
PCI_GATED_RST#
QSW
PG 24
U9C1
SW7J1
R=0
R=0
PG 31
FWH
PG 34
SIO
PG 45
PG 33
U87A4A
4.401
Reset Map
A
48 50Monday, September 15, 2003
Intel 855GM/GME CRB <Doc>
Title
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Date: Sheet
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Project: