Design Guide

R
4 Intel
®
855GM/855GME Chipset Platform Design Guide
4.1.4.8.
Voltage Translation Logic ............................................................... 55
4.1.5. Processor RESET# Signal ............................................................................ 55
4.1.5.1. Processor RESET# Routing Example............................................ 57
4.1.6. Processor and GMCH Host Clock Signals .................................................... 57
4.1.7. Processor GTLREF Layout and Routing Recommendations........................ 58
4.1.8. AGTL+ I/O Buffer Compensation .................................................................. 60
4.1.8.1. Processor AGTL+ I/O Buffer Compensation .................................. 60
4.1.9. Intel Pentium M / Intel Celeron M Front Side Bus Strapping and
Debug Port..................................................................................................... 63
4.1.10. Processor V
CCSENSE
/V
SSSENSE
Design Recommendations.............................. 64
4.2. Intel System Validation Debug Support ........................................................................ 64
4.2.1. ITP Support.................................................................................................... 65
4.2.1.1. Background/Justification................................................................. 65
4.2.1.2. Implementation ............................................................................... 65
4.2.2. Intel Pentium M / Intel Celeron M Processor Logic Analyzer Support
(FSB LAI) ....................................................................................................... 65
4.2.2.1. Background/Justification................................................................. 65
4.2.2.2. Implementation ............................................................................... 66
4.2.3. Intel Pentium M / Intel Celeron M Processor On-Die Logic Analyzer
Trigger (ODLAT) Support .............................................................................. 66
4.3. Onboard Debug Port Routing Guidelines ..................................................................... 66
4.3.1. ITP Signal Routing Guidelines....................................................................... 66
4.3.1.1. ITP Signal Routing Example........................................................... 69
4.3.1.2. ITP_CLK Routing to ITP700FLEX Connector ................................ 70
4.3.1.3. ITP700FLEX Design Guidelines for Production Systems .............. 72
4.3.2. Recommended ITP Interposer Debug Port Implementation ......................... 72
4.3.2.1. ITP_CLK Routing to ITP Interposer................................................ 72
4.3.2.2. ITP Interposer Design Guidelines for Production Systems ............ 73
4.3.3. Logic Analyzer Interface (LAI) ....................................................................... 74
4.3.3.1. Mechanical Considerations ............................................................ 74
4.3.3.2. Electrical Considerations ................................................................ 74
5. Intel
®
Mobile Voltage Positioning IV General Description.......................................................... 75
6. System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration ..................... 76
6.1. Length Matching and Length Formulas......................................................................... 77
6.2. Package Length Compensation .................................................................................... 78
6.3. Topologies and Routing Guidelines .............................................................................. 78
6.3.1. Clock Signals – SCK[5:0], SCK#[5:0] ............................................................ 78
6.3.2. Clock Topology Diagram ............................................................................... 78
6.3.3. Memory Clock Routing Guidelines ................................................................ 79
6.3.3.1. Clock Length Matching Requirements ........................................... 80
6.3.3.2. Clock Reference Lengths ............................................................... 81
6.3.3.3. Clock Package Length Table ......................................................... 82
6.3.3.4. Clock Routing Example .................................................................. 82
6.3.4. Data Signals – SDQ[71:0], SDM[8:0], SDQS[8:0] ......................................... 83
6.3.4.1. Data Bus Topology ......................................................................... 84
6.3.4.2. SDQS to Clock Length Matching Requirements ............................ 85
6.3.4.3. Data to Strobe Length Matching Requirements ............................. 87
6.3.4.4. SDQ to SDQS Mapping.................................................................. 88
6.3.4.5. SDQ/SDQS Signal Package Lengths............................................. 89
6.3.4.6. Memory Data Routing Example...................................................... 91
6.3.5. Control Signals – SCKE[3:0], SCS#[3:0] ....................................................... 91
6.3.5.1. Control Signal Topology ................................................................. 92