Design Guide

Intel Pentium M/Celeron M Front Side Bus Design Guidelines

Intel

855GM/855GME Chipset Platform Design Guide 51

dampening resistor R1 in Topology 1B. Thus, it is important to note that R1 will no longer be required

in such a topology.

Figure 10. Routing Illustration for Topology 1B

VCCP

Rtt

CPU

ICH4-M

(or sys. receiver)

Table 11. Layout Recommendations for Topology 1B

L1 L2 L3 R1 Rtt Transmission Line

0.5” – 12.0” 0” – 3.0” 0” – 3.0” 56 Ω ± 5% 56 Ω ± 5% Micro-strip

0.5” – 12.0” 0” – 3.0” 0” – 3.0” 56 Ω ± 5% 56 Ω ± 5% Strip-line

4.1.4.3. Topology 1C: Open Drain (OD) Signals Driven by the Processor –

PROCHOT#

The Topology 1C OD signal PROCHOT# should adhere to the following routing and layout

recommendations. Table 12 lists the recommended routing requirements for the PROCHOT# signal of

the processor. The routing guidelines allow the signal to be routed as either a micro-strip or strip-line

using 55 Ω ± 15% characteristic trace impedance. Figure 11 shows the recommended implementation

for providing voltage translation between the processor’s PROCHOT# signal and a system receiver that

utilizes a 3.3-V interface voltage (shown as V_IO_RCVR). The receiver at the output of the voltage

translation circuit can be any system receiver that can function properly with the PROCHOT# signal

given the nature and usage model of this pin. PROCHOT# is capable of toggling hundreds of times per

second to signal a hot temperature condition.

Series resistor Rs is a component of the voltage translation logic and serves as a driver isolation resistor.

Rs is shown separated by distance L3 from the first bipolar junction transistor (BJT), Q1, to emphasize

the placement of Rs with respect to Q1. The placement of Rs a distance L3 before the Q1 BJT is a

specific implementation of the generalized voltage translator circuit shown in Figure 16. Rs should be

placed at the beginning of the T-split from the PROCHOT# signal. The pull-up voltage for termination

resistor Rtt is VCCP (1.05 V).