Design Guide

R
6 Intel
®
855GM/855GME Chipset Platform Design Guide
7.3.5.3.
Control to Clock Length Matching Requirements......................... 143
7.3.5.4. Control Group Package Length Table.......................................... 144
7.3.6. Command Signals – SMAA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#.. 145
7.3.6.1. Command Topology ..................................................................... 145
7.3.6.2. Command Topology Routing Guidelines...................................... 148
7.3.6.3. Command Topology Length Matching Requirements.................. 149
7.3.6.4. Command Group Package Length Table..................................... 151
7.3.7. CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1] .............................................. 152
7.3.7.1. CPC Signal Topology ................................................................... 153
7.3.7.2. CPC Signal Routing Guidelines ................................................... 155
7.3.7.3. CPC to Clock Length Matching Requirements............................. 156
7.3.7.4. CPC Group Package Length Table.............................................. 157
8. Integrated Graphics Display Port ............................................................................................. 159
8.1. Analog RGB/CRT Guidelines...................................................................................... 159
8.1.1. RAMDAC/Display Interface ......................................................................... 159
8.1.2. Reference Resistor (REFSET) .................................................................... 159
8.1.3. RAMDAC Board Design Guidelines ............................................................ 160
8.1.4. RAMDAC Routing Guidelines...................................................................... 161
8.1.5. DAC Power Requirements .......................................................................... 163
8.1.6. HSYNC and VSYNC Design Considerations .............................................. 164
8.1.7. DDC and I2C Design Considerations.......................................................... 164
8.2. LVDS Transmitter Interface......................................................................................... 164
8.2.1. LVDS Length Matching Constraints ............................................................ 165
8.2.2. LVDS Package Length Compensation........................................................ 165
8.2.3. LVDS Routing Guidelines............................................................................ 165
8.3. Digital Video Out Port.................................................................................................. 168
8.3.1. Length Matching Requirements................................................................... 168
8.3.2. Package Length Compensation .................................................................. 169
8.3.3. DVOB and DVOC Routing Guidelines ........................................................ 169
8.3.4. DVOB and DVOC Assumptions, Definitions, and Specifications ................ 171
8.3.5. DVOB and DVOC Simulation Method ......................................................... 172
8.4. DVOB and DVOC port Flexible (Modular) Design ...................................................... 173
8.4.1. DVOB and DVOC Module Design ............................................................... 173
8.4.1.1. Generic Connector Model............................................................. 173
8.5. DVO GMBUS and DDC Interface Considerations ...................................................... 174
8.5.1. Leaving the GMCH DVOB or DVOC Port Unconnected ............................. 175
8.5.2. Miscellaneous Input Signals and Voltage Reference.................................. 175
8.5.3. PM_SUS_CLK/AGP_PIPE# Design Consideration .................................... 175
9. AGP Port Design Guidelines.................................................................................................... 177
9.1. AGP Interface .............................................................................................................. 177
9.1.1. AGP Interface Signal Groups ...................................................................... 177
9.2. AGP Routing Guidelines ............................................................................................. 179
9.2.1. 1x Timing Domain Routing Guidelines ........................................................ 179
9.2.1.1. Trace Length Requirements for AGP 1X...................................... 179
9.2.1.2. Trace Spacing Requirements....................................................... 179
9.2.1.3. Trace Length Mismatch ................................................................ 179
9.2.2. 2x/4x Timing Domain Routing Guidelines ................................................... 180
9.2.2.1. Trace Length Requirements for AGP 2X/4X ................................ 180
9.2.2.2. Trace Spacing Requirements....................................................... 180
9.2.2.3. Trace Length Mismatch Requirements ........................................ 181
9.2.3. AGP Clock Skew ......................................................................................... 182
9.2.4. AGP Signal Noise Decoupling Guidelines................................................... 182