Design Guide

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Intel® 855GM/855GME Chipset Platform Design Guide 7
9.2.5.
AGP Interface Package Lengths..................................................................183
9.2.6. AGP Routing Ground Reference .................................................................184
9.2.7. Pull-ups ........................................................................................................184
9.2.8. AGP VDDQ and VCC...................................................................................186
9.2.9. VREF Generation for AGP 2.0 (2X and 4X).................................................186
9.2.9.1. 1.5-V AGP Interface (2X/4X).........................................................186
9.2.10. AGP Compensation .....................................................................................186
9.2.11. PM_SUS_CLK/AGP_PIPE# Design Consideration.....................................186
10. Hub Interface ............................................................................................................................187
10.1. Hub Interface Compensation .......................................................................................187
10.2. Hub Interface Data HL[10:0] and Strobe Signals ........................................................188
10.2.1. HL[10:0] and Strobe Signals Internal Layer Routing ...................................188
10.2.2. Terminating HL[11].......................................................................................190
10.3. Hub VREF/VSWING Generation/Distribution ..............................................................190
10.3.1. Single Generation Voltage Reference Divider Circuit..................................190
10.3.2. Locally Generated Voltage Reference Divider Circuit .................................191
10.3.3. Single GMCH and ICH4-M Voltage Generation / Separate Divider
Circuit for VSWING/VREF............................................................................192
10.3.4. Separate GMCH and ICH4-M Voltage Generation / Separate Divider
Circuits for VREF and VSWING...................................................................193
10.4. Hub Interface Decoupling Guidelines ..........................................................................193
11. I/O Subsystem ..........................................................................................................................195
11.1. IDE Interface ................................................................................................................195
11.1.1. Cabling .........................................................................................................195
11.1.2. Primary IDE Connector Requirements.........................................................196
11.1.3. Secondary IDE Connector Requirements....................................................197
11.1.4. Mobile IDE Swap Bay Support.....................................................................198
11.1.4.1. ICH4-M IDE Interface Tri-State Feature .......................................198
11.1.4.2. S5/G3 to S0 Boot Up Procedures for IDE Swap Bay ...................199
11.1.4.3. Power Down Procedures for Mobile Swap Bay ............................199
11.1.4.4. Power Up Procedures After Device “Hot” Swap Completed ........199
11.2. PCI 200
11.3. AC’97 200
11.3.1. AC’97 Routing ..............................................................................................204
11.3.2. Motherboard Implementation .......................................................................205
11.3.2.1. Valid Codec Configurations ..........................................................205
11.3.3. SPKR Pin Configuration...............................................................................205
11.4. USB 2.0 Guidelines and Recommendations ...............................................................206
11.4.1. Layout Guidelines ........................................................................................206
11.4.1.1. General Routing and Placement...................................................206
11.4.1.2. USB 2.0 Trace Separation ............................................................207
11.4.1.3. USBRBIAS Connection.................................................................207
11.4.1.4. USB 2.0 Termination.....................................................................208
11.4.1.5. USB 2.0 Trace Length Pair Matching ...........................................208
11.4.1.6. USB 2.0 Trace Length Guidelines ................................................208
11.4.2. Plane Splits, Voids, and Cut-Outs (Anti-Etch)..............................................208
11.4.2.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)......................209
11.4.2.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) .....................209
11.4.3. USB Power Line Layout Topology ...............................................................209
11.4.4. EMI Considerations......................................................................................210
11.4.4.1. Common Mode Chokes ................................................................210
11.4.5. ESD ..............................................................................................................211