Design Guide

System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration
R
Intel
®
855GM/855GME Chipset Platform Design Guide 79
Figure 33. Memory Clock Routing Topology SCK/SCK#[5:0]
P1
L1
SO-DIM M PADS
D ifferential Pairs
GMCH
P1
L2
R1
GMCH
Pin
L1 L2
6.3.3. Memory Clock Routing Guidelines
Table 24. Clock Signal Group Routing Guidelines
Parameter Definition
Signal Group SCK[5:0] and SCK#[5:0]
Topology Differential Pair Point to Point
Reference Plane Ground Referenced
Single Ended Trace Impedance ( Zo )
(see note on trace width below)
42
Ω +/-15% (for reference only)
Differential Mode Impedance (Zdiff)
(see note on trace width below)
70
Ω +/- 15% (for reference only)
Nominal Trace Width
(see note on trace width and exceptions for
breakout region below)
Inner Layers: 7 mils
Outer Layers: 8 mils (pin escapes only)
Nominal Pair Spacing (edge to edge)
(see exceptions for breakout region below)
Inner Layers: 4 mils
Outer Layers: 5 mils (pin escapes only)
Minimum Pair to Pair Spacing (see
exceptions for breakout region below)
20 mils
Minimum Serpentine Spacing 20 mils
Minimum Spacing to Other DDR Signals
(see exceptions for breakout region below)
20 mils
Minimum Isolation Spacing to non-DDR Signals 25 mils
Maximum Via Count 2 (per side)
Package Length Range – P1 1000 mils +/- 350mils (Refer to Table 25 for exact lengths.)
Trace Length Limits – L1 Max = 300 mils (breakout segment)
Total MB Length Limits – L1 + L2
Min = 0.5”
Max = 5.0”
Total Length – P1 + L1 + L2
Total length target is determined by placement (see Figure 33)
Total length for SO-DIMM0 group = X0 (see Figure 34)
Total length for SO-DIMM1 group = X1 (see Figure 34)
SCK to SCK# Length Matching Match total length to +/- 10 mils (see Section 6.3.3.1)
Clock to Clock Length Matching (Total Length)
Match all SO-DIMM0 clocks to X0 +/- 25 mils (see Figure 34)
Match all SO-DIMM1 clocks to X1 +/- 25 mils (see Figure 34)