Design Guide

R
8 Intel
®
855GM/855GME Chipset Platform Design Guide
11.4.6.
USB Selective Suspend............................................................................... 211
11.5. I/O APIC (I/O Advanced Programmable Interrupt Controller) ..................................... 212
11.6. SMBus 2.0/SMLink Interface....................................................................................... 212
11.6.1. SMBus Architecture and Design Considerations ........................................ 214
11.6.1.1. SMBus Design Considerations..................................................... 214
11.6.1.2. General Design Issues/Notes....................................................... 214
11.6.1.3. High Power/Low Power Mixed Architecture ................................. 214
11.6.1.4. Calculating the Physical Segment Pull-Up Resistor..................... 215
11.7. FWH 216
11.7.1. FWH Decoupling.......................................................................................... 216
11.7.2. In Circuit FWH Programming....................................................................... 216
11.7.3. FWH INIT# Voltage Compatibility................................................................ 216
11.7.4. FWH V
PP
Design Guidelines........................................................................ 217
11.7.5. FWH INIT# Assertion/Deassertion Timings................................................. 217
11.8. RTC 218
11.8.1. RTC Crystal ................................................................................................. 219
11.8.2. External Capacitors ..................................................................................... 220
11.8.3. RTC Layout Considerations ........................................................................ 221
11.8.4. RTC External Battery Connections.............................................................. 221
11.8.5. RTC External RTCRST# Circuit .................................................................. 222
11.8.6. V
BIAS
DC Voltage and Noise Measurements ............................................... 223
11.8.7. SUSCLK....................................................................................................... 223
11.8.8. RTC-Well Input Strap Requirements ........................................................... 223
11.9. Internal LAN Layout Guidelines .................................................................................. 223
11.9.1. Footprint Compatibility ................................................................................. 224
11.9.2. Intel
®
82801DBM ICH4-M – LAN Connect Interface Guidelines................. 225
11.9.2.1. Bus Topologies............................................................................. 226
11.9.2.1.1. LAN On Motherboard Point-To-Point Interconnect .... 226
11.9.2.2. Signal Routing and Layout ........................................................... 226
11.9.2.3. Crosstalk Consideration ............................................................... 227
11.9.2.4. Impedances .................................................................................. 227
11.9.2.5. Line Termination........................................................................... 227
11.9.2.6. Terminating Unused LAN Connect Interface Signals................... 227
11.9.3. Intel 82562ET / Intel 82562 EM Guidelines................................................. 227
11.9.3.1. Guidelines for Intel 82562ET / Intel 82562EM Component
Placement 228
11.9.3.2. Crystals and Oscillators................................................................ 228
11.9.3.3. Intel 82562ET / Intel 82562EM Termination Resistors................. 228
11.9.3.4. Critical Dimensions....................................................................... 229
11.9.3.4.1. Distance from Magnetics Module to
RJ-45 (Distance A) ..................................................... 229
11.9.3.4.2. Distance from Intel 82562ET / 82562ET to
Magnetics Module (Distance B) ................................. 230
11.9.3.5. Reducing Circuit Inductance ........................................................ 230
11.9.3.5.1. Terminating Unused Connections .............................. 230
11.9.3.5.2. Termination Plane Capacitance ................................. 230
11.9.4. Intel 82562ET/EM Disable Guidelines......................................................... 231
11.9.5. Design and Layout Consideration for Intel 82540EP / 82551QM ............... 232
11.9.6. General Intel 82562ET / 82562EM / 82551QM / 82540EP Differential Pair
Trace Routing Considerations ..................................................................... 232
11.9.6.1.1. Trace Geometry and Length ...................................... 234
11.9.6.1.2. Signal Isolation ........................................................... 234