Design Guide
R
Intel® 855GM/855GME Chipset Platform Design Guide 9
11.9.6.1.3.
Magnetics Module General Power and Ground Plane
Considerations ............................................................234
11.9.6.2. Common Physical Layout Issues..................................................236
11.10. Power Management Interface......................................................................................237
11.10.1. SYS_RESET# Usage Model........................................................................237
11.10.2. PWRBTN# Usage Model .............................................................................237
11.10.3. Power Well Isolation Control Strap Requirements.......................................237
11.11. CPU I/O Signal Considerations ...................................................................................238
12. Platform Clock Routing Guidelines...........................................................................................239
12.1. System Clock Groups ..................................................................................................239
12.2. Clock Group Topologies and Routing Constraints ......................................................240
12.2.1. Host Clock Group.........................................................................................241
12.2.1.1. Host Clock Group General Routing Guidelines ............................243
12.2.1.2. Clock to Clock Length Matching and Compensation....................243
12.2.1.3. Host Clock to CLK66 Routing Recommendations........................243
12.2.1.4. EMI Constraints.............................................................................244
12.2.2. CLK66 Clock Group .....................................................................................245
12.2.3. CLK33 Clock Group .....................................................................................247
12.2.4. PCI Clock Group ..........................................................................................248
12.2.5. CLK14 Clock Group .....................................................................................249
12.2.6. DOTCLK Clock Group..................................................................................250
12.2.7. SSCCLK Clock Group..................................................................................251
12.2.8. USBCLK Clock Group..................................................................................252
12.3. CK-408 Clock Updates for Intel Pentium M Processor and
Intel Celeron M Processor Platforms...........................................................................253
12.4. CK-408 PWRDWN# Signal Connections ....................................................................253
13. Intel 855GM/GME Chipset Based System Power Delivery Guidelines....................................255
13.1. Definitions ....................................................................................................................255
13.2. Platform Power Requirements.....................................................................................255
13.2.1. Platform Power Delivery Architectural Block Diagram.................................256
13.3. Voltage Supply.............................................................................................................257
13.3.1. Power Management States..........................................................................257
13.3.2. Power Supply Rail Descriptions...................................................................257
13.4. 855GM/GME Chipset Based System Power-Up Sequence........................................258
13.4.1. Processor Power Sequence Requirement...................................................258
13.4.2. GMCH Power Sequencing Requirements ...................................................258
13.4.3. ICH4-M Power Sequencing Requirements..................................................259
13.4.3.1. 3.3/1.5 V Power Sequencing ........................................................261
13.4.3.2. V
5REF
Sequencing..........................................................................261
13.4.3.3. V
5REFSUS
Design Guidelines...........................................................262
13.4.4. DDR Memory Power Sequencing Requirements ........................................263
13.5. Intel 855GM/GME Chipset Based System Power Delivery Guidelines.......................264
13.5.1. 855GM/GME Chipset GMCH Decoupling Guidelines..................................265
13.5.1.1. GMCH VCCSM Decoupling ..........................................................266
13.5.1.2. DDR Memory Device VDD Decoupling ........................................266
13.5.1.3. DDR VTT Decoupling Placement and Layout Guidelines ............266
13.5.2. DDR Memory Power Delivery Design Guidelines........................................266
13.5.2.1. 2.5-V Power Delivery Guidelines ..................................................267
13.5.2.2. GMCH and DDR SMVREF Design Recommendations................267
13.5.2.3. DDR SMRCOMP Resistive Compensation ..................................268
13.5.2.4. DDR VTT Termination ..................................................................268