Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
Specification Update 25
Errata
L1. Transaction Is Not Retired after BINIT#
Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the
snoop phase it should be retried and the locked sequence restarted. However, if
BINIT# is also asserted during this transaction, the transaction will not be retried.
Implication: When this erratum occurs, locked transactions will not be retried.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L2. Invalid Opcode 0FFFh Requires a ModRM Byte
Problem: Some invalid opcodes require a ModRM byte and other following bytes, while others
do not. The invalid opcode 0FFFh did not require a ModRM in previous generation
microprocessors such as Pentium
®
II or Pentium III processors, but it is required in
the Intel
®
Pentium
®
4 processors, and the Prescott processor.
Implication: The use of an invalid opcode 0FFFh without the ModRM byte may result in a page or
limit fault on the Prescott processor. When this erratum occurs, locked transactions
will not be retried.
Workaround: To avoid this erratum use ModRM byte with invalid 0FFFh opcode
Status: For the steppings affected, see the Summary Tables of Changes.