Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
26 Specification Update
L3. Processor May Hang Due to Speculative Page Walks to NonExistent
System Memory
Problem: A load operation issued speculatively by the processor that misses the Data
Translation Lookaside Buffer (DTLB) results in a page walk. A branch instruction older
than the load retires so that this load operation is now in the mispredicted branch
path. Due to an internal boundary condition, in some instances the load is not
canceled before the page walk is issued.
The Page Miss Handler (PMH) starts a speculative page-walk for the Load and issues
a cacheable load of the Page Directory Entry (PDE). This PDE load returns data that
points to a page table entry in uncacheable (UC) memory. The PMH issues the PTE
Load to UC space, which is issued on the Front Side Bus. No response comes back for
this load PTE operation since the address is pointing to system memory, which does
not exist.
This load to non-existent system memory causes the processor to hang because
other bus requests are queued up behind this UC PTE load, which never gets a
response. If the load was accessing valid system memory, the speculative page-walk
would successfully complete and the processor would continue to make forward
progress.
Implication: Processor may hang due to speculative page walks to non-existent system memory.
Workaround: Page directories and page tables in UC memory space must point to system
memory that exists
Status: For the steppings affected, see the Summary Tables of Changes
L4. Memory Type of the Load Lock Different from Its Corresponding
Store Unlock
Problem: A use-once protocol is employed to ensure that the processor in a multi-agent
system may access data that is loaded into its cache on a Read-for-Ownership
operation at least once before it is snooped out by another agent. This protocol is
necessary to avoid a multi-agent livelock scenario in which the processor cannot gain
ownership of a line and modify it before that data is snooped out by another agent.
In the case of this erratum, split load lock instructions incorrectly trigger the use-
once protocol. A load lock operation accesses data that splits across a page boundary
with both pages of WB memory type. The use-once protocol activates and the
memory type for the split halves get forced to UC. Since use-once does not apply to
stores, the store unlock instructions go out as WB memory type. The full sequence on
the bus is: locked partial read (UC), partial read (UC), partial write (WB), locked
partial write (WB). The use-once protocol should not be applied to load locks
Implication: When this erratum occurs, the memory type of the load lock will be different than the
memory type of the store unlock operation. This behavior (Load Locks and Store
Unlocks having different memory types) does not however introduce any functional
failures such as system hangs or memory corruption
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes