Intel Celeron Processor for the PGA370 Socket up to 1.40 GHz on 0.13 Micron Process Datasheet

20 Datasheet
Intel
®
Celeron
®
Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
on the model 68xh based on 0.18 micron process core processor. By connecting the VID25mV
signal to the Vss pin, it will disable the 25 mV stepping granularity output and the regulator will
resort to 50 mV stepping increment. The voltage regulator or VRM must supply the voltage that is
requested or disable itself.
In addition to the new signal “VID25mV”, the processor will introduce a second new signal labeled
as “VTT_PWRGD”. The VTT_PWRGD signal informs the platform that the VID and BSEL
signals are stable and should be sampled. During Power-up, the VID signals will be in an
indeterminate state for a small period of time. The voltage regulator or the VRM should not latch
the VID signals until the VTT_PWRGD signal is asserted by the VRM and sampled active. The
assertion of the VTT_PWRGD signal indicates the VID signals are stable and are driven to the
final state by the processor. Refer to Figure 14 for power-up timing sequence for the
VTT_PWRGD and the VID signals.
NOTES:
1. 0 = Processor pin connected to V
SS. and 1 = Open on processor; may be pulled up to TTL V
IH
(3.3 V max) on
baseboard.
Table 3. Voltage Identification Definition
1
VID25mV VID3 VID2 VID1 VID0 Vcc
CORE
00100 1.05
10100 1.075
00011 1.10
10011 1.125
00010 1.15
10010 1.175
00001 1.20
10001 1.225
00000 1.25
10000 1.275
01111 1.30
11111 1.325
01110 1.35
11110 1.375
01101 1.40
11101 1.425
01100 1.45
11100 1.475
01011 1.50
11011 1.525
01010 1.55
11010 1.575
01001 1.60
11001 1.625
01000 1.65
11000 1.675
00111 1.70
10111 1.725
00110 1.75
10110 1.775
00101 1.80
10101 1.825