Intel Celeron Processor for the PGA370 Socket up to 1.40 GHz on 0.13 Micron Process Datasheet

Datasheet 81
Intel
®
Celeron
®
Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
NOTE: Synchronous assertion with active TDRY# ensures synchronization.
LINT[1:0] High Asynch CMOS Input APIC enabled mode
NMI High Asynch CMOS Input APIC disabled mode
NCHCTRL N/A Asynch Power/Other
PICCLK High — APIC Clock Always
PREQ# Low Asynch CMOS Input Always
PWRGOOD High Asynch CMOS Input Always
RESET# Low BCLK AGTL Input Always
RESET2# Low BCLK AGTL Input
RSP# Low BCLK AGTL Input Always
RTTCTRL N/A Asynch Power/Other
SLEWCTRL N/A Asynch Power/Other
SLP# Low Asynch CMOS Input During Stop-Grant state
SMI# Low Asynch CMOS Input
STPCLK# Low Asynch CMOS Input
TCK High — TAP Input
TDI High TCK TAP Input
TMS High TCK TAP Input
TRST# Low Asynch TAP Input
VTT_PWRGD High Asynch Power/Other
Table 42. Input Signals (Sheet 2 of 2)
Name Active Level Clock Signal Group Qualified
Table 43. Input/Output Signals (Single Driver)
Name Active Level Clock Signal Group Qualified
A[35:3]# Low BCLK AGTL I/O ADS#, ADS#+1
ADS# Low BCLK AGTL I/O Always
AP[1:0]# Low BCLK AGTL I/O ADS#, ADS#+1
BP[3:2]# Low BCLK AGTL I/O Always
BPM[1:0]# Low BCLK AGTL I/O Always
BR0# Low BCLK AGTL I/O Always
D[63:0]# Low BCLK AGTL I/O DRDY#
DBSY# Low BCLK AGTL I/O Always
DEP[7:0]# Low BCLK AGTL I/O DRDY#
DRDY# Low BCLK AGTL I/O Always
LOCK# Low BCLK AGTL I/O Always
REQ[4:0]# Low BCLK AGTL I/O ADS#, ADS#+1
RP# Low BCLK AGTL I/O ADS#, ADS#+1
RS[2:0]# Low BCLK AGTL Input Always
TRDY# Low BCLK AGTL Input