Intel Celeron Processor on 0.13 Micron Process in the 478-Pin Package Datasheet

Intel
®
Celeron
®
Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 5
Figures
1 VCCVID Pin Voltage and Current Requirements................................................15
2 Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................17
3 Phase Lock Loop (PLL) Filter Requirements ......................................................17
4 VCC Static and Transient Tolerance...................................................................24
5 ITPCLKOUT[1:0] Output Buffer Diagram ............................................................27
6 AC Test Circuit ....................................................................................................32
7 TCK Clock Waveform..........................................................................................33
8 Differential Clock Waveform................................................................................33
9 Differential Clock Crosspoint Specification..........................................................34
10 System Bus Common Clock Valid Delay Timings...............................................34
11 System Bus Reset and Configuration Timings....................................................35
12 Source Synchronous 2X (Address) Timings .......................................................35
13 Source Synchronous 4X Timings........................................................................36
14 Power Up Sequence ...........................................................................................37
15 Power Down Sequence.......................................................................................37
16 Test Reset Timings .............................................................................................38
17 THERMTRIP# Power Down Sequence...............................................................38
18 ITPCLKOUT Valid Delay Timing .........................................................................38
19 FERR#/PBE# Valid Delay Timing .......................................................................39
20 TAP Valid Delay Timing ......................................................................................39
21 BCLK Signal Integrity Waveform.........................................................................42
22 Low-to-High System Bus Receiver Ringback Tolerance.....................................43
23 High-to-Low System Bus Receiver Ringback Tolerance.....................................43
24 Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD
and TAP Buffers..................................................................................................44
25 High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD
and TAP Buffers..................................................................................................44
26 Maximum Acceptable Overshoot/Undershoot Waveform ...................................49
27 Exploded View of Processor Components on a System Board ..........................51
28 Processor Package .............................................................................................52
29 Processor Cross-Section and Keep-In................................................................53
30 Processor Pin Detail............................................................................................53
31 IHS Flatness Specification ..................................................................................54
32 Processor Markings.............................................................................................55
33 Processor Pinout Coordinates (Top View, Left Side) ..........................................56
34 Processor Pinout Coordinates (Top View, Right Side)........................................57
35 Example Thermal Solution (Not to Scale) ...........................................................81
36 Guideline Locations for Case Temperature (TC) Thermocouple Placement ......83
37 Stop Clock State Machine...................................................................................86
38 Mechanical Representation of the Boxed Processor ..........................................91
39 Side View Space Requirements for the Boxed Processor ..................................92
40 Top View Space Requirements for the Boxed Processor ...................................93
41 Boxed Processor Fan Heatsink Power Cable Connector Description.................95
42 MotherBoard Power Header Placement Relative to Processor Socket ..............96
43 Boxed Processor Fan Heatsink Airspace Keep-Out Requirements
(Side 1 View).......................................................................................................97
44 Boxed Processor Fan Heatsink Airspace Keep-Out Requirements
(Side 2 View).......................................................................................................98
45 Boxed Processor Fan Heatsink Set Points .........................................................99