Specification Update

Errata
Specification Update 53
W48. Certain Performance Monitoring Counters Related to Bus,
L2 Cache and Power Management Are Inaccurate
Problem: All Performance Monitoring Counters in the ranges 21H-3DH and 60H-
7FH may have inaccurate results up to ±7.
Implication: There may be a small error in the affected counts.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W49. Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions and
May Push the Wrong Address Onto the Stack
Problem: Normally, when the processor encounters a Segment Limit or Canonical
Fault due to code execution, a #GP (General Protection Exception) fault
is generated after all higher priority Interrupts and exceptions are
serviced. Due to this erratum, if RSM (Resume from System
Management Mode) returns to execution flow that results in a Code
Segment Limit or Canonical Fault, the #GP fault may be serviced before a
higher priority Interrupt or Exception (e.g. NMI (Non-Maskable Interrupt),
Debug break(#DB), Machine Check (#MC), etc.). If the RSM attempts to
return to a non-canonical address, the address pushed onto the stack for
this #GP fault may not match the non-canonical address that caused the
fault
.
Implication: Operating systems may observe a #GP fault being serviced before higher
priority Interrupts and Exceptions. Intel has not observed this erratum on
any commercially available software
.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W50. A Write to an APIC Register Sometimes May Appear to
Have Not Occurred
Problem: With respect to the retirement of instructions, stores to
the uncacheable memory-based APIC register space are handled in a
non-synchronized way. For example, if an instruction that masks the
interrupt flag (e.g., CLI) is executed soon after an uncacheable write to
the Task Priority Register (TPR) that lowers the APIC priority, the
interrupt masking operation may take effect before the actual priority
has been lowered. This may cause interrupts whose priority is lower
than the initial TPR, but higher than the final TPR, to not be serviced
until the interrupt enabled flag is finally set, i.e., by STI instruction.
Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but
may delay their service.