Specification Update

ManualsBrandsIntel ManualsOtherIntel Celeron Processor 566 MHz, 128K Cache, 66 MHz FSB

Table Of Contents

Errata

54 Specification Update

Workaround: This non-synchronization can be avoided by issuing an APIC register read after the

APIC register write. This will force the store to the APIC register before any

subsequent instructions are executed. No commercial operating system is known to be

impacted by this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.