Specification Update

Errata
64 Specification Update
Workaround: Operating systems should not allow A20M# to be enabled if the masking of address
bit 20 could be applied to an address that references a large page. A20M# is normally
only used with the first megabyte of memory.
Status: For the steppings affected, see the Summary Tables of Changes.
W75. CPUID Extended Feature Does Not Report Intel® Thermal
Monitor 2 Support Correctly
Problem: Processors with no support for Intel® Thermal Monitor 2 will falsely
report support for Intel Thermal Monitor 2 as enabled by setting TM2
(bit 8) in the Extended Feature Flag returned in ECX when executing
CPUID with EAX=01H.
Implication: Extended Feature Flag TM2 cannot be used to identify processors where
Intel Thermal Monitor 2 is disabled.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W76. Removed erratum due to redundancy
W77. Removed – See Erratum W32
W78. Premature Execution of a Load Operation Prior to
Exception Handler Invocation
Problem: If any of the below circumstances occur it is possible that the load portion
of the instruction will have executed before the exception handler is
entered.
1. If an instruction that performs a memory load causes a code segment limit
violation
2. If a waiting X87 floating-point instruction or MMX™ technology (MMX) instruction
that performs a memory load has a floating-point exception pending
3. If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a
memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point
Top-of-Stack (FP TOS) not equal to 0, or a DNA exception pending
Implication: In normal code execution where the target of the load operation is to
write back memory there is no impact from the load being prematurely
executed, nor from the restart and subsequent re-execution of that
instruction by the exception handler. If the target of the load is to
uncached memory that has a system side-effect, restarting the
instruction may cause unexpected system behavior due to the
repetition of the side-effect. Particularly, while CR0.TS [bit 3] is set, a
MOVD/MOVQ with MMX/XMM register operands may issue a memory
load before getting the DNA exception.
Workaround: Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when