Specification Update

Errata
66 Specification Update
W79. Performance Monitoring Events for Retired Instructions
(C0H) May Not Be Accurate
Problem: The INST_RETIRED performance monitor may miscount retired
instructions as follows:
• Repeat string and repeat I/O operations are not counted when a hardware
interrupt is received during or after the last iteration of the repeat flow.
• VMLAUNCH and VMRESUME instructions are not counted.
• HLT and MWAIT instructions are not counted. The following instructions, if
executed during HLT or MWAIT events, are also not counted:
⎯ a) RSM from a C-state SMI during an MWAIT instruction.
⎯ b) RSM from an SMI during a HLT instruction.
Implication: There may be a smaller than expected value in the INST_RETIRED
performance monitoring counter. The extent to which this value is
smaller than expected is determined by the frequency of the above
cases.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W80. #GP Fault Is NOT Generated on Writing
IA32_MISC_ENABLE [34] When Execute Disable Bit Is Not
Supported
Problem: #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a
processor which does not support Execute Disable Bit functionality.
Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without
generating a fault.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W81. This erratum has been removed. It does not apply to the
Celeron M processor. Please see the Summary Tables of
Changes for more information.
W82. Removed; See Erratum W26