Specification Update

Errata
Specification Update 67
W83. Writing Shared Unaligned Data That Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a
Memory Ordering Issue
Problem: Software which is written so that multiple agents can modify the same
shared unaligned memory location at the same time may experience a
memory ordering issue if multiple loads access this shared data shortly
thereafter. Exposure to this problem requires the use of a data write
which spans a cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has
not observed this erratum with any commercially-available software or
system.
Workaround: Software should ensure at least one of the following is true when modifying shared
data by multiple agents:
• The shared data is aligned
• Proper semaphores or barriers are used in order to prevent concurrent data
accesses.
Status: For affected steppings see the Summary Tables of Changes.
W84. MSRs Actual Frequency Clock Count (IA32_APERF) or
Maximum Frequency Clock Count (IA32_MPERF) May
Contain Incorrect Data after a Machine Check Exception
(MCE)
Problem: When an MCE occurs during execution of a RDMSR instruction for MSRs
Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency
Clock Count (IA32_MPERF), the current and subsequent RDMSR
instructions for these MSRs may contain incorrect data.
Implication: After an MCE event, accesses to the IA32_APERF and IA32_MPERF
MSRs may return incorrect data. A subsequent reset will clear this
condition.
Workaround: None identified.
Status: For affected steppings see the Summary Tables of Changes.
W85. Incorrect Address Computed for Last Byte of
FXSAVE/FXRSTOR Image Leads to Partial Memory Update
Problem: A partial memory state save of the 512-byte FXSAVE image or a partial
memory state restore of the FXRSTOR image may occur if a memory
address exceeds the 64-kB limit while the processor is operating in 16-
bit mode or if a memory address exceeds the 4-GB limit while the
processor is operating in 32-bit mode.