Specification Update

Errata
68 Specification Update
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit
violation as expected but the memory state may be only partially saved
or restored.
Workaround: Software should avoid memory accesses that wrap around the respective 16-bit and
32-bit mode memory limits.
Status: For affected steppings see the Summary Tables of Changes.
W86. Values for LBR/BTS/BTM Will Be Incorrect after an Exit
from SMM
Problem: After a return from SMM (System Management Mode), the CPU will
incorrectly update the LBR (Last Branch Record) and the BTS (Branch
Trace Store), hence rendering their data invalid. The corresponding
data if sent out as a BTM on the system bus will also be incorrect.
Note: This issue would only occur when one of the 3 above-mentioned
debug support facilities are used.
Implication: The value of the LBR, BTS, and BTM immediately after an RSM
operation should not be used.
Workaround: None identified.
Status: For affected steppings see the Summary Tables of Changes.
W87. Using Memory Type Aliasing with Memory Types WB/WT
May Lead to Unpredictable Behavior
Problem: Memory type aliasing occurs when a single physical page is mapped to two
or more different linear addresses, each with different memory type.
Memory type aliasing with the memory types WB and WT may cause
the processor to perform incorrect operations leading to unpredictable
behavior.
Implication: Software that uses aliasing of WB and WT memory types may observe
unpredictable behavior. Intel chipset-based platforms are not affected
by this erratum.
Workaround: None identified. Intel does not support the use of WB and WT page memory type
aliasing.
Status: For affected steppings see the Summary Tables of Changes.
W88. Performance Monitoring Event FP_ASSIST May Not Be
Accurate
Problem: Performance monitoring event FP_ASSIST (11H) may be inaccurate as
assist events will be counted twice per actual assist in the following
specific cases:
• FADD and FMUL instructions with a Not a Number (NaN) operand and a memory
operand.