Specification Update

Errata
Specification Update 93
W145. Performance Monitoring Event CPU_CLK_UNHALTED.REF
May Not Count Clock Cycles According to the Processors
Operating Frequency
Problem: Performance Counter MSR_PERF_FIXED_CTR2 (MSR 30BH) that counts
CPU_CLK_UNHALTED.REF clocks, should count these clock cycles at a
constant rate that is determined by the maximum resolved boot
frequency, as programmed by BIOS. Due to this erratum, the rate is
instead, set by the maximum core-clock to bus-clock ratio of the
processor, as indicated by hardware.
Implication: No functional impact as a result of this erratum. If the maximum
resolved boot frequency as programmed by BIOS is different from the
frequency implied by the maximum core-clock to bus-clock ratio of the
processor as indicated by hardware, then the following effects may be
observed.
Workaround: Performance Monitoring Event CPU_CLK_UNHALTED.REF will count at a rate different
than the TSC (Time Stamp Counter).
When running a system with several processors that have different maximum core-
clock to bus-clock ratios, CPU_CLK_UNHALTED.REF monitoring events at each
processor will be counted at different rates and therefore will not be comparable.
Calculate the ratio of the rates at which the TSC and the CPU_CLK_UNHALTED.REF
performance monitoring event count (this can be done by measuring simultaneously
their counted value while executing code) and adjust the CPU_CLK_UNHALTED.REF
event count to the maximum resolved boot frequency using this ratio.
Status: For the steppings affected, see the Summary Tables of Changes.
W146. Performance Monitoring Event BR_INST_RETIRED May
Count CPUID Instructions as Branches
Problem: Performance monitoring event BR_INST_RETIRED (C4H) counts retired
branch instructions. Due to this erratum, two of its sub-events
mistakenly count for CPUID instructions as well. Those sub events are:
BR_INST_RETIRED.PRED_NOT_TAKEN (Umask 01H) and
BR_INST_RETIRED.ANY (Umask 00H).
Implication: The count value returned by the performance monitoring event
BR_INST_RETIRED.PRED_NOT_TAKEN or BR_INST_RETIRED.ANY may
be higher than expected. The extent of over counting depends on the
occurrence of CPUID instructions, while the counter is active.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.