Specification Update

Errata
96 Specification Update
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W153. A WB Store Following a REP STOS/MOVS of FXSAVE May Lead to
Memory-Ordering Violations
Problem: Under certain conditions, as described in the Software Developers Manual
section "Out-of-Order Stores For String Operations in Pentium 4, Intel
Xeon, and P6 Family Processors", the processor may perform REP
MOVS or REP STOS as write combining stores (referred to as “fast
strings”) for optimal performance. FXSAVE may also be internally
implemented using write combining stores. Due to this erratum, stores
of a WB (write back) memory type to a cache line previously written by
a preceding fast string/FXSAVE instruction may be observed before
string/FXSAVE stores.
Implication: A write-back store may be observed before a previous string or FXSAVE
related store. Intel has not observed this erratum with any
commercially available software.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes. §
W154. RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution
Problem: RSM instruction execution, under certain conditions triggered by a
complex sequence of internal processor micro-architectural events, may
lead to processor hang, or unexpected instruction execution results.
Implication: In the above sequence, the processor may live lock or hang, or RSM
instruction may restart the interrupted processor context through a
nondeterministic EIP offset in the code segment, resulting in
unexpected instruction execution, unexpected exceptions or system
hang. Intel has not observed this erratum with any commercially
available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
W155: Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown
Problem: According to the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A, “Exception and Interrupt Reference”, if another exception occurs while
attempting to call the double-fault handler, the processor enters shutdown mode.
However due to this erratum, only Contributory Exceptions and Page Faults will cause
a triple fault shutdown, whereas a benign exception may not.