Specification Update

Errata
44 Specification Update
AM76 Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count
Some Decoded Instructions
Problem: MACRO_INSTS.DECODED performance monitoring counter (Event 0AAH, Umask 01H)
counts the number of macro instructions decoded, but not necessarily retired. The
event is undercounted when the decoded instructions are a complete loop iteration
that is decoded in one cycle and the loop is streamed by the LSD (Loop Stream
Detector), as described in the Optimizing the Front End section of the Intel® 64 and
IA-32 Architectures Optimization Reference Manual.
Implication: The count value returned by the performance monitoring counter
MACRO_INST.DECODED may be lower than expected. The degree of undercounting is
dependent on the occurrence of loop iterations that are decoded in one cycle and
whether the loop is streamed by the LSD while the counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AM77 Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted
Incorrectly for PMULUDQ Instruction
Problem: Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL (Event select 0B3H,
Umask 01H) counts the number of SIMD packed multiply micro-ops executed. The
count for PMULUDQ micro-ops may be lower than expected. No other instruction is
affected.
Implication: The count value returned by the performance monitoring event
SIMD_UOP_TYPE_EXEC.MUL may be lower than expected. The degree of undercount
depends on actual occurrences of PMULUDQ instructions, while the counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.