Specification Update

Errata
48 Specification Update
AM85 ODLAT Does Not Match on Written Data When the FSB Ratio is 6:1
Problem: Normally, the ODLAT (On-Die Logic Analyzer) debug mechanism triggers when an FSB
(Front Side Bus) transaction that matches the ODLAT_ARM MSRs completes. When a
trigger occurs, one of the BPMx# pins is driven for 1 FSB clock cycle. Due to this
erratum, when the FSB ratio is 6:1 and ODLAT is programmed to match data it will
not trigger on write transactions.
Implication: When the FSB ratio is 6:1 ODLAT will not trigger a match if it is programmed on data
match and the transaction is a write. ODLAT will correctly trigger a match on read
transactions and on write transactions that do not require a data match. Address and
Type matching are unaffected.
Workaround: When operating at the 6:1 FSB ratio avoid programming ODLAT to trigger a match on
written data.
Status: For the steppings affected, see the Summary Tables of Changes.
AM86 Store Ordering May be Incorrect between WC and WP Memory Types
Problem: According to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual,
Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain
the WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type
stores do. Due to this erratum, WP stores may not drain the WC buffers.
Implication: Memory ordering may be violated between WC and WP stores.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AM87 Fixed Function Performance Counters MSR_PERF_FIXED_CTR1 (30AH) and
MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared When the Processor is Reset
Problem: The Fixed Function Performance Counters that count the number of core cycles and
reference cycles when the core is not in a halt state are not cleared when the
processor is reset.
Implication: The MSR_PERF_FIXED_CTR1 and MSR_PERF_FIXED_CTR2 counters may contain
unexpected values after reset.
Workaround: BIOS can workaround this erratum by clearing the counters at processor initialization
time.
Status: For the steppings affected, see the Summary Tables of Changes.