Intel Celeron D Processor 300 Sequence on 90 nm Process

Summary Tables of Changes
Specification Update 11
NO. B1 C0 D0 E0 LE0
1
G1 LG1
1
Plans Errata
L1 X X X X X X X No Fix Transaction is not retried after BINIT#
L2 X X X X X X X No Fix
Invalid opcode 0FFFH requires a ModRM
byte
L3 X X X X X X X No Fix
Processor may hang due to Speculative
Page Walks to Non-Existent System Memory
L4 X X X X X X X No Fix
Memory type of the load lock different from
its corresponding store unlock
L5 X X X X X X X No Fix
Machine check architecture error
reporting and recovery may not
work as expected
L6 X X X X X X X No Fix
Debug mechanisms may not function as
expected
L7 X X X X X X X No Fix
Cascading of performance counters does not
work correctly when forced overflow is
enabled
L8 X X X X X X X No Fix
EMON event counting of X87 loads may not
work as expected
L9 X X X X X X X No Fix
System bus interrupt messages without
data and which receive a HardFailure
response may hang the processor
L10 X X X X X X X No Fix
Processor flags #PF instead of #AC on an
unlocked CMPXCHG8B instruction
L11 X X X X X X X No Fix
FSW may not be completely restored after
page fault on FRSTOR or FLDENV
instructions
L12 X X X X X X X No Fix
Processor Issues Inconsistent Transaction
Size Attributes for Locked Operation
L13 X X X X X X X No Fix
When the processor is in the System
Management Mode (SMM), Debug Registers
may be fully writeable
L14 X X X X X X X No Fix
The Processor May Issue Front Side Bus
Transactions up to 6 Clocks after RESET# is
Asserted
L15 X X X X X X X No Fix
Processor may hang under certain
frequencies and 12.5% STPCLK# duty cycle
L16 X X X X X X X No Fix
System may hang if a fatal cache error
causes Bus Write Line (BWL) transaction to
occur to the same cache line address as an
outstanding Bus Read Line (BRL) or Bus
Read-Invalidate Line (BRIL)
L17 X X X X X X X No Fix
A Write to an APIC Register Sometimes May
Appear to Have Not Occurred