Intel Celeron D Processor 300 Sequence on 90 nm Process

Summary Tables of Changes
12 Specification Update
NO. B1 C0 D0 E0 LE0
1
G1 LG1
1
Plans Errata
L18 X X X X X X X No Fix
The Processor May Issue Multiple Code
Fetches to the Same Cacheline for Systems
with Slow Memory
L19 X X X X X X X No Fix
Parity Error in the L1 Cache may cause the
processor to hang
L20 X X Fixed
BPM4# Signal Not Being Asserted According
to Specification
L21 X X X X X X X No Fix
Front Side Bus Machine Checks May be
Reported as a Result of On-Going
Transactions during Warm Reset.
L22 X X X Fixed
A 16-bit Address Wrap Resulting from a
Near Branch (Jump or Call) May Cause an
Incorrect Address to Be Reported to the
#GP Exception Handler
L23 X X X X X X X No Fix
Locks and SMC Detection May Cause the
Processor to Temporarily Hang
L24 X X X X X X X No Fix
L2 Cache ECC Machine Check
Errors May be erroneously Reported after an
Asynchronous RESET# Assertion
L25 X X Fixed
PWRGOOD and TAP Signals Maximum Input
Hysteresis Higher Than Specified
L26 X X Fixed
Some Front Side Bus I/O Specifications are
not Met
L27 X X Fixed
Incorrect Physical Address Size Returned by
CPUID Instruction
L28 X X X X X X X No Fix
Incorrect Debug Exception (#DB) May Occur
When a Data Breakpoint is set on an FP
Instruction
L29 X X X X X X X No Fix
xAPIC May Not Report Some Illegal Vector
Errors
L30 X X X X X X X No Fix
Memory Aliasing of Pages as Uncacheable
Memory Type and Write Back (WB) May
Hang the System
L31 X X X X X X X No Fix
Interactions Between the Instruction
Translation Lookaside Buffer (ITLB) and the
Instruction Streaming Buffer May Cause
Unpredictable Software Behavior
L32 X X Fixed
Changes to CR3 Register do not Fence
Pending Instruction Page Walks
L33 X X Fixed
The State of the Resume Flag (RF Flag) in a
Task-State Segment (TSS) May be Incorrect
L34 X X X X X X X No Fix
Processor Provides a 4-Byte Store Unlock
After an 8-Byte Load Lock