Intel Celeron D Processor 300 Sequence on 90 nm Process

Summary Tables of Changes
Specification Update 13
NO. B1 C0 D0 E0 LE0
1
G1 LG1
1
Plans Errata
L35 X X X X X X X No Fix
Writing the Local Vector Table (LVT)
when an Interrupt is Pending May Cause an
Unexpected Interrupt
L36 X X Fixed
CPUID Instruction May Report Incorrect L2
Associativity in Leaf 0x80000006
L37 X X X X X
Plan
Fix
Execution of IRET or INTn Instructions
May Cause Unexpected System Behavior
L38 X X Fixed
The FP_ASSIST EMON Event May Return an
Incorrect Count
L39 X X X X X X X No Fix
Machine Check Exceptions May not Update
Last-Exception Record MSRs (LERs)
L40 X X X X X X X No Fix
MOV CR3 Performs Incorrect Reserved Bit
Checking When in PAE Paging
L41 X X X X X X X No Fix
Stores to Page Tables May Not Be Visible to
Pagewalks for Subsequent Loads Without
Serializing or Invalidating the Page Table
Entry
L42 X X X X X X X No Fix
Data Breakpoints on the High Half of a
Floating Point Line Split may not be
Captured
L43 X X X Fixed
A Split Store Memory Access May Miss
a Data Breakpoint
L44 X Fixed
EFLAGS.RF May be Incorrectly Set After an
IRET Instruction
L45 X X Fixed
Read for Ownership and Simultaneous Fetch
May Cause the Processor to Hang
L46 X Fixed
Writing the Echo TPR Disable Bit in
IA32_MISC_ENABLE May Cause a #GP Fault
L47 X X Fixed
Cache Lock with Simultaneous Invalidate
external snoop and SMC check May Cause
the Processor to Hang
L48 X X Fixed
IRET Instruction Performing Task Switch
May Not Serialize the Processor Execution
L49 X X X Fixed
Incorrect Access Controls to
MSR_LASTBRANCH_0_FROM_LIP MSR
Registers
L50 X X X Fixed
Recursive Page Walks May Cause a System
Hang
L51 X Fixed
When the Execute Disable Bit Function is
Enabled a Page-fault in a Mispredicted
Branch May Result in a Page-fault Exception
L52 X Fixed
Execute Disable Bit Set with AD Assist Will
Cause Livelock