Intel Celeron D Processor 300 Sequence on 90 nm Process

Summary Tables of Changes
14 Specification Update
NO. B1 C0 D0 E0 LE0
1
G1 LG1
1
Plans Errata
L53 X Fixed
The Execute Disable Bit Fault May be
Reported Before Other Types of Page Fault
When Both Occur
L54 X Fixed
Execute Disable Mode may Cause Livelock
L55 X X X X X X X No Fix
Checking of Page Table Base Address May
Not Match the Address Bit Width Supported
by the Platform
L56 X X X X X X X No Fix
The IA32_MCi_STATUS MSR May
Improperly Indicate that Additional MCA
Information Has Been Captured
L57 X X X X X X X No Fix
With TF (Trap Flag) Asserted, FP Instruction
That Triggers an Unmasked FP Exception
May Take Single Step Trap Before
Retirement of Instruction
L58 X X X Fixed
MCA Corrected Memory Hierarchy Error
Counter May Not Increment Correctly
L59 X X X X X X X No Fix
BTS(Branch Trace Store) and PEBS(Precise
Event Based Sampling) May Update
Memory outside the BTS/PEBS Buffer
L60 X X X X X X X No Fix
Memory Ordering Failure May Occur with
Snoop Filtering Third Party Agents after
Issuing and Completing a BWIL (Bus Write
Invalidate Line) or BLW (Bus Locked Write)
Transaction
L61 X X X X X X X No Fix
Control Register 2 (CR2) Can be Updated
during a REP MOVS/STOS Instruction with
Fast Strings Enabled
L62 X X X X X
Plan
Fix
TPR (Task Priority Register) Updates during
Voltage Transitions of Power Management
Events May Cause a System Hang
L63 X X X X X X X
Plan
Fix
It is Possible That Two specific Invalid
Opcodes May Cause Unexpected Memory
Accesses
L64 X X
Plan
Fix
VERR/VERW Instructions May Cause #GP
Fault when Descriptor is in Non-canonical
Space
L65 X Fixed
The Base of a Null Segment May be Non-
zero on a Processor Supporting Intel®
Extended Memory 64 Technology (Intel®
EM64T)
Φ
L66 X Fixed
Upper 32 Bits of FS/GS with Null Base May
not get Cleared in Virtual-8086 Mode on
Processors with Intel® Extended Memory 64
Technology (Intel® EM64T) Enabled