Intel Celeron D Processor 300 Sequence on 90 nm Process

Summary Tables of Changes
Specification Update 15
NO. B1 C0 D0 E0 LE0
1
G1 LG1
1
Plans Errata
L67 X X No Fix
Processor May Fault when the Upper 8 Bytes
of Segment Selector is Loaded From a Far
Jump Through a Call Gate via the Local
Descriptor Table
L68 X X No Fix
Loading a Stack Segment with a
Selector that References a Non-canonical
Address can Lead to a #SS Fault on a
Processor Supporting Intel® Extended
Memory 64 Technology (Intel® EM64T)
L69 X X No Fix
FXRSTOR May Not Restore Non-canonical
Effective Addresses on Processors with
Intel® Extended Memory 64 Technology
(Intel® EM64T) Enabled
L70 X X
Plan
Fix
The Base of an LDT (Local Descriptor Table)
Register May be Non-zero on a Processor
Supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
L71 X X No Fix
REP STOS/MOVS Instructions with RCX
>=2^32 May Cause a System Hang
L72 X X
Plan
Fix
An REP MOVS or an REP STOS Instruction
with RCX >= 2^32 May Fail to Execute to
Completion or May Write to Incorrect
Memory Locations on Processors Supporting
Intel® Extended Memory 64 Technology
(Intel® EM64T)
L73 X X
Plan
Fix
An REP LODSB or an REP LODSD or an REP
LODSQ Instruction with RCX >= 2^32 May
Cause a System Hang on Processors
Supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
L74 X X No Fix
A Data Access which Spans Both the
Canonical and the Non-Canonical Address
Space May Hang the System
L75 X X No Fix
A 64-Bit Value of Linear Instruction Pointer
(LIP) May be Reported Incorrectly in the
Branch Trace Store (BTS) Memory Record or
in the Precise Event Based Sampling (PEBS)
Memory Record
L76 X X X X X X X No Fix
At Core-to-bus Ratios of 16:1 and
Above Defer Reply Transactions with Non-
zero REQb Values, May Cause a Front Side
Bus Stall
L77 X X X X X X X No Fix
IRET under Certain Conditions May Cause an
Unexpected Alignment Check Exception
L78 X X X X X X X No Fix
Using 2M/4M Pages When A20M# Is
Asserted May Result in Incorrect Address
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