Intel Celeron D Processor 300 Sequence on 90 nm Process

Summary Tables of Changes
16 Specification Update
NO. B1 C0 D0 E0 LE0
1
G1 LG1
1
Plans Errata
L79 X X X X X X X No Fix
Writing Shared Unaligned Data that Crosses
a Cache Line without Proper Semaphores or
Barriers May Expose a Memory Ordering
Issue
L80 X X X X X X X No Fix
The
IA32_MC0_STATUS and IA32_MC1_STATUS
Overflow Bit is not set when Multiple Un-
correctable Machine Check Errors Occur at
the Same Time
L81 X X X X X X X No Fix
Debug Status Register (DR6) Breakpoint
Condition Detected Flags May be set
Incorrectly
L82 X X X X X X X No Fix
A VM Exit Occurring in IA-32e Mode May
Not Produce a VMX Abort When Expected
NOTES:
1. Only applies to processors in LGA775 Land Pkg
No. Plan Specification Clarifications
L1 THERMTRIP# De-assertion Clarification for the 478-pin Package.
L2 THERMTRIP# De-assertion Clarification for the 775-pin Package.
No. Plan Documentation Changes
There are no Documentation Changes in this Specification Update revision.
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