Intel Celeron D Processor 300 Sequence on 90 nm Process

Identification Information
Specification Update 17
Identification Information
The Intel
®
Celeron
®
D Processor on 90 nm Process and in the 478-Pin Package and
the Intel
®
Celeron
®
D Processor on 90 nm Process and in the 775 Land Package may
be identified by the following values.
Family
1
Model
2
1111b 0011b
1111b 0100b
NOTES:
1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the
generation field of the Device ID register accessible through Boundary Scan.
2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX
register after the CPUID instruction is executed with a 1 in the EAX register, and the model
field of the Device ID register accessible through Boundary Scan.
Table 1. Intel
®
Celeron
®
D Processor on 90 nm Process and in the 478-Pin Package
and the Intel
®
Celeron
®
D Processor on 90 nm Process and in the 775 Land Package
Identification Information
S-Spec
Core
Stepping
Processor
Signature
Processor
Number
Core
Freq
(GHz)
Data
Bus
Freq
(MHz)
L2
Cache
Size
Processor
Package
Revision
Package And
Revision
Notes
SL7WS D0 0F34h 315 2.26 533 256KB 02
478-pin micro-PGA
with 35.0 x 35.0 mm
FC-mPGA4 package
1
SL7XY E0 0F41h 315 2.26 533 256KB 02
478-pin micro-PGA
with 35.0 x 35.0 mm
FC-mPGA4 package
1
SL7C4 C0 0F33h 320 2.40 533 256KB 02
478-pin micro-PGA
with 35.0 x 35.0 mm
FC-mPGA4 package
1
SL7JV D0 0F34h 320 2.40 533 256KB 02
478-pin micro-PGA
with 35.0 x 35.0 mm
FC-mPGA4 package
1
SL7C5 C0 0F33h 325 2.53 533 256KB 02
478-pin micro-PGA
with 35.0 x 35.0 mm
FC-mPGA4 package
1