Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
30 Specification Update
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes
L7. Cascading of Performance Counters Does Not Work Correctly When
Forced Overflow Is Enabled
Problem: The performance counters are organized into pairs. When the CASCADE bit of the
Counter Configuration Control Register (CCCR) is set, a counter that overflows will
continue to count in the other counter of the pair. The FORCE_OVF bit forces the
counters to overflow on every non-zero increment. When the FORCE_OVF bit is set,
the counter overflow bit will be set but the counter no longer cascades
Implication: The performance counters do not cascade when the FORCE_OVF bit is set
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes
L8. EMON Event Counting of x87 Loads May Not Work As Expected
Problem: If a performance counter is set to count x87 loads and floating-point exceptions are
unmasked, the FPU Operand (Data) Pointer (FDP) may become corrupted
Implication: When this erratum occurs, FPU Operand (Data) Pointer (FDP) may become corrupted
Workaround: This erratum will not occur with floating point exceptions masked. If floating-point
exceptions are unmasked, then performance counting of x87 loads should be
disabled
Status: For the steppings affected, see the Summary Tables of Changes
L9. System Bus Interrupt Messages without Data and Which Receive a
HardFailure Response May Hang the Processor
Problem: When a System Bus agent (processor or chipset) issues an interrupt transaction
without data onto the System Bus, and the transaction receives a HardFailure
response, a potential processor hang can occur. The processor, which generates an
inter-processor interrupt (IPI) that receives HardFailure response, will still log the
MCA error event cause as HardFailure, even if the APIC causes a hang. Other
processors, which are true targets of the IPI, will also hang on hardfailure-without-
data, but will not record an MCA HardFailure event as a cause. If a HardFailure
response occurs on a System Bus interrupt message with data, the APIC will
complete the operation so as not to hang the processor
Implication: The processor may hang
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes