Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
Specification Update 31
L10. Processor Flags #PF Instead of #AC on an Unlocked CMPXC8B
Instruction
Problem: If a data page fault (#PF) and alignment check fault (#AC) both occur for an
unlocked CMPXC8B instruction, then #PF will be flagged
Implication: Software that depends #AC before #PF will be affected since #PF is flagged in this
case
Workaround: Remove the software’s dependency on the fact that #AC has precedence over
#PF. Alternately, if the reload is due to a not present page, reload the page in the
page fault handler and then restart the faulting instruction
Status: For the steppings affected, see the Summary Tables of Changes
L11. FSW May Not Be Completely Restored after Page Fault on FRSTOR or
FLDENV Instructions
Problem: If the FPU operating environment or FPU state (operating environment and register
stack) being loaded by an FLDENV or FRSTOR instruction wraps around a 64-Kbyte or
4-Gbyte boundary and a page fault (#PF) or segment limit fault (#GP or #SS) occurs
on the instruction near the wrap boundary, the upper byte of the FPU status word
(FSW) might not be restored. If the fault handler does not restart program execution
at the faulting instruction, stale data may exist in the FSW
Implication: When this erratum occurs, stale data will exist in the FSW
Workaround: Ensure that the FPU operating environment and FPU state do not cross 64-Kbyte
or 4-Gbyte boundaries. Alternately, ensure that the page fault handler restarts
program execution at the faulting instruction after correcting the paging problem
Status: For the steppings affected, see the Summary Tables of Changes
L12. Processor Issues Inconsistent Transaction Size Attributes for Locked
Operation
Problem: When the processor is in the Page Address Extension (PAE) mode and detects the
need to set the Access and/or Dirty bits in the page directory or page table entries,
the processor sends an 8 byte load lock onto the System Bus. A subsequent 8 byte
store unlock is expected, but instead a 4 byte store unlock occurs. Correct data is
provided since only the lower bytes change, however external logic monitoring the
data transfer may be expecting an 8-byte store unlock
Implication: No known commercially available chipsets are affected by this erratum
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes