Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
32 Specification Update
L13. When the Processor Is in the System Management Mode (SMM),
Debug Registers May Be Fully Writeable
Problem: When in System Management Mode (SMM), the processor executes code and stores
data in the SMRAM space. When the processor is in this mode and writes are made to
DR6 and DR7, the processor should block writes to the reserved bit locations. Due to
this erratum, the processor may not block these writes. This may result in invalid
data in the reserved bit locations
Implication: Reserved bit locations within DR6 and DR7 may become invalid
Workaround: Software may perform a read/modify/write when writing to DR6 and DR7 to
ensure that the value in the reserved bits are maintained
Status: For the steppings affected, see the Summary Tables of Changes
L14. The Processor May Issue Front Side Bus Transactions up to 6 Clocks
after RESET# is Asserted
Problem: The processor may issue transactions beyond the documented 3 Front Side Bus
(FSB) clocks and up to 6 FSB clocks after RESET# is asserted in the case of a warm
reset. A warm reset is where the chipset asserts RESET# when the system is
running
Implication: The processor may issue transactions up to 6 FSB clocks after RESET# is asserted
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes
L15. Processor May Hang Under Certain Frequencies and 12.5% STPCLK#
Duty Cycle
Problem: If a system de-asserts STPCLK# at a 12.5% duty cycle, and the processor is running
below 2 GHz, and the processor thermal control circuit (TCC) on-demand clock
modulation is active, the processor may hang. This erratum does not occur under the
automatic mode of the TCC
Implication: When this erratum occurs, the processor will hang
Workaround: If use of the on-demand mode of the processor's TCC is desired in conjunction
with STPCLK# modulation, then assure that STPCLK# is not asserted at a 12.5%
duty cycle
Status: For the steppings affected, see the Summary Tables of Changes