Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
34 Specification Update
Problem: Systems with long latencies on returning code fetch data from memory e.g. BIOS
ROM, may cause the processor to issue multiple fetches to the same cache line, once
per each instruction executed
Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a
result of this erratum, in a commercially available system
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes
L19. Parity Error in the L1 Cache May Cause the Processor to Hang
Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is
possible that the processor may hang while trying to evict the line
Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this
erratum with any commercially available software
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes
L20. BPM4# Signal Not Being Asserted According to Specification
Problem: BPM4# signal is not being asserted according to the specification. This may cause
incorrect operation of In-Target Debuggers particularly at higher FSB frequencies
Implication: In-Target Debuggers may not function at higher than 133/533 MHz FSB
Workaround: One method is to reduce the FSB common clock frequency to 133 MHz or lower.
For higher FSB speeds, In-Target Debuggers have a built-in function (test2010) that
tells the hardware to ignore BPM4# assertions. This may degrade the debugger
performance but will give correct results
Status: For the steppings affected, see the Summary Tables of Changes
L21. Front Side Bus Machine Checks May be Reported as a Result of On-
Going Transactions during Warm Reset
Problem: Processor Front Side Bus (FSB) protocol/signal integrity machine checks may be
reported if the transactions are initiated or in-progress during a warm reset. A warm
reset is where the chipset asserts RESET# when the system is running
Implication: The processor may log FSB protocol/signal integrity machine checks if transactions
are allowed to occur during RESET# assertions
Workaround: BIOS may clear FSB protocol/signal integrity machine checks for
systems/chipsets which do not block new transactions during RESET# assertions
Status: For the steppings affected, see the Summary Tables of Changes