Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
36 Specification Update
L24. L2 Cache ECC Machine Check Errors May be erroneously Reported
after an Asynchronous RESET# Assertion
Problem: Problem: Machine check status MSRs may incorrectly report the following L2 Cache
ECC machine-check errors when cache transactions are in-flight and RESET# is
asserted:
• Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153)
• L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145)
Implication: Uncorrected or corrected L2 ECC machine check errors may be erroneously reported.
Intel has not observed this erratum on any commercially available system
Workaround: When a real run-time L2 Cache ECC Machine Check occurs, a corresponding valid
error will normally be logged in the IA32_MC0_STATUS register. BIOS may clear
IA32_MC2_STATUS and/or IA32_MC1_STATUS for these specific errors when
IA32_MC0_STATUS does not have its VAL flag set
Status: For the steppings affected, see the Summary Tables of Changes
L25. PWRGOOD and TAP Signals Maximum Input Hysteresis Higher Than
Specified
Problem: The maximum input hysteresis for the PWRGOOD and TAP input signals are specified
at 350 mV. The actual value could be as high as 800 mV
Implication: The PWRGOOD and TAP inputs may switch at different levels than previously
documented specifications. Intel has not observed any issues in validation or
simulation as a result of this erratum
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes at the beginning of
this section