Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
Specification Update 37
L26. Some Front Side Bus I/O Specifications Are Not Met.
Problem: Problem: The following front side bus I/O specifications are not met:
• The VIH(min) for the GTL+ signals is specified as GTLREF + (0.10 * VCC) [V].
• The VIH(min) for the Asynchronous GTL+ signals is specified as Vcc/2 + (0.10 *
VCC) [V].
• Common Clock Output Valid Delay (min) is specified as -0.250 ns.
• Common Clock Input Setup Time is specified as 0.700 ns.
• Source Synchronous Input Setup Time to Strobe is specified as 0.150 ns.
• Source Synchronous Input Hold Time to Strobe is specified as 0.150 ns
Implication: This erratum can cause functional failures depending upon system bus activity. It can
manifest itself as data parity, address parity, and/or machine check errors
Workaround: Due to this erratum, the system should meet the following voltage levels and
processor timings:
• The VIH(min) for GTL+ signals is now GTLREF + (0.20 * VCC) [V].
• The VIH(min) for the Asynchronous GTL+ signals is now Vcc/2 + (0.20 * VCC)
[V].
• Common Clock Output Valid Delay (min) is now -0.300 ns.
• Common Clock Input Setup Time is now 0.900 ns.
• Source Synchronous Input Setup Time to Strobe is now 0.350 ns.
• Source Synchronous Input Hold Time to Strobe is now 0.350 ns
Status: For the steppings affected, see the Summary Tables of Changes
L27. Incorrect Physical Address Size Returned by CPUID Instruction
Problem: The CPUID instruction Function 80000008H (Extended Address Sizes Function)
returns the address sizes supported by the processor in the EAX register. This