Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
38 Specification Update
Function returns an incorrect physical address size value of 40 bits. The correct
physical address size is 36 bits
Implication: Function 80000008H returns an incorrect physical address size value of 40 bits
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes
L28. Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint
Is Set on an FP Instruction
Problem: The default Microcode Floating Point Event Handler routine executes a series of loads
to obtain data about the FP instruction that is causing the FP event. If a data
breakpoint is set on the instruction causing the FP event, the load in the microcode
routine will trigger the data breakpoint resulting in a Debug Exception
Implication: An incorrect Debug Exception (#DB) may occur if data breakpoint is placed on an FP
instruction. Intel has not observed this erratum with any commercially available
software or system
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes
L29. xAPIC May Not Report Some Illegal Vector Errors
Problem: The local xAPIC has an Error Status Register, which records all errors. The bit 6 (the
Receive Illegal Vector bit) of this register, is set when the local xAPIC detects an
illegal vector in a received message. When an illegal vector error is received on the
same internal clock that the error status register is being written (due to a previous
error), bit 6 does not get set and illegal vector errors are not flagged
Implication: The xAPIC may not report some Illegal Vector errors when they occur at
approximately the same time as other xAPIC errors. The other xAPIC errors will
continue to be reported
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes
L30. Memory Aliasing of Pages as Uncacheable Memory Type and Write
Back (WB) May Hang the System
Problem: When a page is being accessed as either Uncacheable (UC) or Write Combining (WC)
and WB, under certain bus and memory timing conditions, the system may
loop in a