Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
40 Specification Update
Problem: The RF flag is normally used for code breakpoint management during debug of an
application. It is not typically used during normal program execution. Code
breakpoints or single step debug behavior in the presence of hardware task switches,
therefore, may be unpredictable as a result of this erratum. This erratum has not
been observed in commercially available software
Implication: The RF flag is normally used for code breakpoint management during debug of an
application. It is not typically used during normal program execution. Code
breakpoints or single step debug behavior in the presence of hardware task switches,
therefore, may be unpredictable as a result of this erratum. This erratum has not
been observed in commercially available software
Workaround: It is possible for the BIOS to contain a workaround for this erratum. (BIOS
workaround may exist for C step only)
Status: For the steppings affected, see the Summary Tables of Changes
L34. Processor Provides a 4-Byte Store Unlock After an 8-Byte Load Lock
Problem: When the processor is in the Page Address Extension (PAE) mode and detects the
need to set the Access and/or Dirty bits in the page directory or page table entries,
the processor sends an 8 byte load lock onto the system bus. A subsequent 8 byte
store unlock is expected, but instead a 4 byte store unlock occurs. Correct data is
provided since only the lower bytes change, however external logic monitoring the
data transfer may be expecting an 8 byte load lock
Implication: No known commercially available chipsets are affected by this erratum
Workaround: None identified at this time
Status: For the steppings affected, see the Summary Tables of Changes
L35. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be
taken on the new interrupt vector even if the mask bit is set
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no Interrupt
Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does
not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service
register and mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it,
even if that vector was programmed as masked. This ISR routine must do an EOI to
clear any unexpected interrupts that may occur. The ISR associated with
the spurious vector does not generate an EOI, therefore the spurious vector should
not be used when writing the LVT.