Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
Specification Update 41
Status: For the steppings affected, see the Summary Tables of Changes
L36. CPUID Instruction May Report Incorrect L2 Associativity in Leaf
0x80000006
Problem: L2 associativity reported by CPUID with EAX=80000006H instruction may be
incorrect.
Implication: Software may see an incorrect L2 associativity when viewed via CPUID with
EAX=80000006H, however, when viewed via CPUID with EAX=4H the associativity
value is correct.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L37. Execution of IRET or INTn Instructions
May Cause Unexpected System Behavior
Problem: There is a small window of time, requiring alignment of many internal micro
architectural events, during which the speculative execution of the IRET or INTn
instructions in protected or IA-32e mode may result in unexpected software or
system behavior.
Implication: This erratum may result in unexpected instruction execution, events, interrupts or a
system hang when the IRET instruction is executed. The execution of the INTn
instruction may cause debug breakpoints to be missed.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L38. The FP_ASSIST EMON Event May Return an Incorrect Count
Problem: The performance monitoring event, FP_ASSIST, may incorrectly calculate the number
of events if denormals or SSE loads are encountered.
Implication: When this erratum occurs, the FP_ASSIST event may not calculate the correct
number of events. As a result, performance optimization software such as Intel
®
VTune™ Performance Analyzer may not be able to take advantage of certain
scenarios.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.