Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
42 Specification Update
L39. Machine Check Exceptions May Not Update Last-Exception Record
MSRs (LERs)
Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check
Exceptions occur.
Implication: When this erratum occurs, the LER may not contain information relating to the
machine check exception. They will contain information relating to the exception prior
to the machine check exception.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L40. MOV CR3 Performs Incorrect Reserved Bit Checking When in PAE
Paging
Problem: The MOV CR3 instruction should perform reserved bit checking on the upper
unimplemented address bits. This checking range should match the address width
reported by CPUID instruction 0x8000008. This erratum applies whenever PAE is
enabled.
Implication: Software that sets the upper address bits on a MOV CR3 instruction and expects a
fault may fail. This erratum has not been observed with commercially available
software.
Workaround: None.
Status: For the steppings affected, see the Summary Tables of Changes.
L41. Stores to Page Tables May Not Be Visible to Pagewalks for
Subsequent Loads without Serializing or Invalidating the Page Table
Entry
Problem: Under rare timing circumstances, a page table load on behalf of a programmatically
younger memory access may not get data from a programmatically older store to the
page table entry if there is not a fencing operation or page translation invalidate
operation between the store and the younger memory access. Refer to the IA-32
Intel
®
Architecture Software Developer's Manual for the correct way to update page
tables. Software that conforms to the Software Developer's Manual will operate
correctly.