Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
Specification Update 43
Implication: If the guidelines in the Software Developer's Manual are not followed, stale data may
be loaded into the processor's Translation Lookaside Buffer (TLB) and used for
memory operations. This erratum has not been observed with any commercially
available software.
Workaround: The guidelines in the IA-32 Intel
®
Architecture Software Developer's Manual
should be followed.
Status: For the steppings affected, see the Summary Tables of Changes.
L42. Data Breakpoints on the High Half of a Floating Point Line Split May
Not Be Captured
Problem: When a floating point load which splits a 64-byte cache line gets a floating point stack
fault, and a data breakpoint register maps to the high line of the floating point load,
internal boundary conditions exist that may prevent the data breakpoint from being
captured.
Implication: When this erratum occurs, a data breakpoint will not be captured.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L43. A Split Store Memory Access May Miss a Data Breakpoint.
Problem: It is possible for a data breakpoint specified by a linear address to be missed during a
split store memory access. The problem can happen with or without paging enabled.
Implication: This erratum may limit the debug capability of a debugger software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of changes.
L44. EFLAGS.RF May Be Incorrectly Set after an IRET Instruction
Problem: EFLAGS.RF is used to disable code breakpoints. After an IRET instruction, EFLAGS.RF
may be incorrectly set or not set depending on its value right before the IRET
instruction.
Implication: A code breakpoint may be missed or an additional code breakpoint may be taken on
next instruction.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.