Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
44 Specification Update
L45. Read for Ownership and Simultaneous Fetch May Cause the
Processor to Hang
Problem: The processor may hang when it attempts to fetch from cache line X and line X+1
simultaneously with a Read for Ownership to cache line X. If the fetch to cache line
X+1 occurs within a small window of time, the processor will detect this as self-
modifying code and the Read for Ownership will be infinitely recycled.
Implication: If this erratum occurs, the processor may hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L46. Writing the Echo TPR Disable Bit in IA32_MISC_ENABLE May Cause a
#GP Fault.
Problem: Writing a ‘1’ to the Echo TPR disable bit (bit 23) in IA32_MISC_ENABLE may
incorrectly cause a #GP fault.
Implication: A #GP fault may occur if the bit is set to a ‘1’.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L47. Cache Lock with Simultaneous Invalidate External Snoop and SMC
Check May Cause the Processor to Hang.
Problem: Under rare timing conditions, the processor may hang when it attempts to execute a
cache lock to a cache line location while simultaneously there is a go to invalidate
external snoop of the same cache line location and the processor is checking for Self-
Modifying Code (SMC) of an unrelated cache line.
Implication: If this erratum occurs, the processor may hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L48. IRET Instruction Performing Task Switch May Not Serialize the
Processor Execution
Problem: When an IRET instruction is executed and the NT (Nested Task) flag in the EFLAGS
register is set, then buffered writes may not be drained to memory before the next
instruction is fetched and executed.
Implication: Executing an IRET instruction when the NT flag in the EFLAGS register is set may not
ensure that all pending memory transactions have completed.