Manualshelf

Intel Celeron D Processor 300 Sequence on 90 nm Process

ManualsBrandsIntel ManualsOtherIntel Celeron Processor 566 MHz, 128K Cache, 66 MHz FSB
41424344454647484950
Errata
Specification Update 45
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L49. Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR
Registers
Problem: When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an
expected #GP fault may not happen.
Implication: A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a #GP
fault.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L50. Recursive Page Walks May Cause a System Hang
Problem: A page walk, accessing the same page table entry multiple times but at different
levels of the page table, which causes the page table entry to have its Access bit set
may result in a system hang.
Implication: When this erratum occurs, the system may experience a hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L51. When the Execute Disable Bit Function is Enabled a Page-fault in a
Mispredicted Branch May Result in a Page-fault Exception
Problem: If a page-fault in a mispredicted branch occurs in the ITLB, it should not be reported
by the processor. However, if the execute disable bit function is enabled
(IA32_EFER.NXE = 1) and there is a page-fault in a mispredicted branch in the ITLB,
a page-fault exception may occur.
Implication: When this erratum occurs, a page-fault exception may occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L52. Execute Disable Bit Set with AD Assist May Cause Livelock
Problem: If Execute Disable Bit is set and the resulting page requires the processor to set the A
and/or D bit (Access and/or Dirty bit) in the PTE, then the processor may livelock.
Implication: When this erratum occurs, the processor may livelock resulting in a system hang or
operating system failure.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.