Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
Specification Update 47
Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and
MISCV bits of the IA32_MCi_STATUS register may be asserted even though the
contents of the IA32_MCi_ADDR and IA32_MCi_MISC MSRs were not properly
captured.
Implication: If this erratum occurs, the MCA information captured in the IA32_MCi_ADDR and
IA32_MCi_MISC may not correspond to the reported machine-check error, even
though the ADDRV and MISCV are asserted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L57. With TF (Trap Flag) Asserted, FP Instruction That Triggers an
Unmasked FP Exception May Take Single Step Trap before Retirement
of Instruction
Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is
possible for external events to occur, including a transition to a lower power state.
When resuming from the lower power state, it may be possible to take the single
step trap before the execution of the original FP instruction completes.
Implication: A Single Step trap will be taken when not expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L58. MCA Corrected Memory Hierarchy Error Counter May Not Increment
Correctly
Problem: An MCA corrected Memory hierarchy error counter can report a maximum of 255
errors. Due to the incorrect increment of the counter, the number of errors reported
may be incorrect.
Implication: Due to this erratum, the MCA counter may report incorrect number of soft errors.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L59. BTS (Branch Trace Store) and PEBS (Precise Event Based Sampling)
May Update Memory outside the BTS/PEBS Buffer
Problem: If the BTS/PEBS buffer is defined such that:
• The difference between BTS/PEBS buffer base and BTS/PEBS absolute maximum
is not an integer multiple of the corresponding record sizes